Divided wordline memory arrangement having overlapping activatio

Details Divided wordline memory arrangement having overlapping activatio Divided wordline memory arrangement having overlapping activatio

1994-11-16

1997-12-16

Lane, Jack A.

Static information storage and retrieval

Read/write circuit

Simultaneous operations

365193, 36523003, 365233, G11C 700, G11C 800

Patent

active

056993005

ABSTRACT:
A semiconductor memory device comprising memory cells arranged in a matrix with plural pairs of bit lines to be column addressed and connected to sense amplifiers, and word lines to be row addressed and divided into divisional word lines. Output signals of sense amplifiers selected by the column addressing are transferred to respective data lines. The divisional word lines are time-sequentially activated corresponding to the row addressing with the activated states of any two sequential divisional word lines overlapped for a fractional time of the full activation time. The sense amplifiers are grouped into plural groups with respective common column addresses. Each group of sense amplifiers have their outputs to be applied to respective data lines connected to a serial/parallel converter.

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