Electrical computers and digital data processing systems: input/ – Input/output data processing – Input/output data buffering
Reexamination Certificate
2000-04-11
2003-09-23
Perveen, Rehana (Department: 2182)
Electrical computers and digital data processing systems: input/
Input/output data processing
Input/output data buffering
C710S056000, C711S154000, C711S163000, C712S035000, C365S189050
Reexamination Certificate
active
06625672
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Technical Field of the Invention
The present invention relates to a device and a method for transporting data through a buffer of the first-in-first-out type.
2. Description of Related Art
Data processing often takes place in integrated circuits. When a stream of data arrives to a data processing unit in a circuit, it is important that each individual data element is treated in a predetermined order and that time can elapse between each process. When a data element arrives, the processing of the element should be independent of when the next element arrives. A buffer may be used for buffering the data elements, and often a buffer of the first-in-first-out type, a so-called FIFO-register, is used. The first element to be written to a FIFO-register is also the first element to be read. Often writing and reading take place at a high rate and FIFO-registers that are used must meet the requirements of rate. It is important that the writing of an element to the FIFO-register, the transport of the element from the inlet to the outlet as well as reading from the FIFO-register are fast. To meet the requirement of rapidity when a buffer is used in an integrated circuit, the buffer is made a part of the integrated circuit. When the buffer constitutes a part of the integrated circuit, writing and reading can be fast. On the other hand, a problem arises in that some silicon surface must be sacrificed on the integrated circuit to give room for the buffer. The problem becomes especially noticeable in the case of the buffer having to be able to store many data elements. In the Japanese Patent Application JP 3212776 the buffer is divided into two parts. The first buffer part is a part of the integrated circuit, and is accordingly present on the same silicon, while the second buffer part is separated from the integrated circuit. The two buffer parts are connected so that data is first written to the second buffer part and is thereafter transported to and read from the first part. The requirement of buffer size is met by the second buffer part, which is not a part of the integrated circuit and accordingly does not take any silicon space. Since the first part is built on the same circuit as the data processing part, data can be accessed from this buffered part without delay. The problem remaining is writing to and reading from the second buffer part, which again is separated from the integrated circuit. Since the second buffer part is separated from the unit from which data is coming in as well as the unit to which data is sent, a delay arises in comparison with the case of these units being present on the same circuit as the buffer. The requirement of rapidity is especially important when the buffer contains only a few elements.
BRIEF DESCRIPTION OF THE INVENTION
The present invention tackles the problem of creating sufficient storage capacity in a buffer of the FIFO type, which is used in an integrated circuit, without taking up unnecessary circuit space and without waiving the requirement of rapidity.
This problem is solved according to the invention by dividing the buffer device into three buffer parts:
An input buffer which is a part of the integrated circuit.
An output buffer which is a part of the integrated circuit.
A storage buffer which is separated from the integrated circuit.
The object of the invention is to create a flexible buffer device which, depending on the data traffic level in the buffer, can be adapted so that requirements of rapidity as well as storage space are met.
In further detail, the buffer device according to the invention comprises a data inlet and a data outlet and also an arrangement for combining the inlet with the outlet via either one of the buffer parts or via a plurality of the buffer parts connected in series. The different FIFO constellations are used at different operating conditions.
The choice of operating condition depends on the number of elements present in the buffer device at the moment and also to which buffer parts these are distributed. The data inlet is combined with the data outlet via different buffer parts by means of a method according to the invention which comprises the following steps:
combining the data inlet with the data outlet via one of the buffers on the integrated circuit;
combining the data inlet with the data outlet via at least two of the buffers, connected in series.
An advantage of the invention is that a large number of data elements can be engaged by the buffer without circuit space for more than a few elements being used on the integrated circuit.
Another advantage of the invention is that writing and reading to/from the buffer can take place at a high rate.
A further advantage is that the time for transporting data can be minimized since access of the separated storage may take place by bursts, or as an alternative, by the width of the bus to the external storage being made large.
Yet another advantage is that a plurality of buffer devices in an effective way can share the same external storage space.
Yet a further advantage of the invention is that conflict situations when reading and writing data can be minimized.
The invention will now be described closer with the aid of preferred embodiments and with reference to attached drawings.
REFERENCES:
patent: 5233603 (1993-08-01), Takeuchi et al.
patent: 5490113 (1996-02-01), Tatosian et al.
patent: 5809557 (1998-09-01), Shemla et al.
patent: 5852826 (1998-12-01), Graunke et al.
patent: 6256218 (2001-07-01), Moon
patent: 6290406 (2001-09-01), Gauthier et al.
patent: 6362649 (2002-03-01), McGowan
patent: 0 886454 (1998-12-01), None
patent: 3-212776 (1991-09-01), None
Pihlgren, O.; International-Type Search Report; Search Request No. SE99/00544; Jan. 25, 2000, pp. 1-4.
Jenkens & Gilchrist P.C.
Perveen Rehana
Telefonaktiebolaget LM Ericsson (publ)
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