Electrical computers and digital processing systems: memory – Address formation – Address mapping
Reexamination Certificate
2000-07-20
2003-08-05
Peikari, B. James (Department: 2186)
Electrical computers and digital processing systems: memory
Address formation
Address mapping
C711S141000, C711S166000, C709S250000
Reexamination Certificate
active
06604185
ABSTRACT:
FIELD OF THE INVENTION
This invention relates to the field of multi-processor, shared-memory computer systems.
BACKGROUND OF THE INVENTION
A computer system typically contains a processor, which is the element of the computer system that controls operation of the computer and executes computer instructions in order to do useful work. This useful work, which is requested by a user of the computer, is often called a “user job.” In order to speed the processing of user jobs, computers have been developed that contain multiple processors, so that a user job can be broken up into pieces, each of which can run concurrently on a different processor. These multiple processors might be contained within one computer system, or they might be distributed across multiple computer systems connected via a network. Just as ten people working concurrently can theoretically dig a ditch ten times faster than one person working alone, ten processors can theoretically complete a user job ten times faster than one processor executing alone.
User jobs need computer memory to store their data, and multiple processors working cooperatively on user jobs typically share memory in order to speed up processing. Since the memory is shared, processors often share common mappings between the user's virtual address space and physical memory. Computers have created the notion of virtual versus physical addresses in order to simplify user jobs, so that they need not worry about where the data is actually stored. To the user job, a virtual address space appears as one uniform, monolithic entity, but the physical data may actually be stored across multiple storage devices of different types in different locations. A processor stores a mapping of its virtual addresses to physical addresses in a place called a “translation lookaside buffer.” When the user job accesses data at a particular virtual address, the processor looks in its translation lookaside buffer to find the actual physical address of the data.
When a user job starts, the processor allocates virtual memory for that job to use. Different jobs need to be using different virtual address spaces, so they don't mistakenly access or modify each other's data. When a user job that is executing cooperatively on multiple processors stops executing because it completes or because it was terminated, the shared, virtual memory needs to be freed or deallocated, so that it is available for use by other jobs.
When one processor determines that user job is stopped, prior multi-processor shared-memory systems have deallocated their own shared memory and then sent a message to other processors that are working cooperatively on the same user job. This message interrupts the other processors in the middle of whatever work they are doing and instructs them to deallocate their shared memory associated with the stopped job. The problem with this message and interrupt-based approach is that it is slow because an interrupt directs the processor to suspend its current operations and to execute a specified routine. It takes time for the processor to save the state of its current operations and to switch to a different sequence of operations.
Thus, there is a need for a solution that will deallocate shared memory in a multi-processor environment that works faster than previous shared memory systems.
SUMMARY OF THE INVENTION
The invention is a method an apparatus for deallocating memory in a multi-processor, shared memory system. In one aspect, a node in the system has a node controller that contains sequencing logic. The sequencing logic receives a command across a network. The sequencing logic translates the received command into a Purge Translation Cache (PTC) instruction and sends the PTC instruction across a bus to a processor. The processor contains bus control logic that receives the PTC instruction and purges a virtual address specified in the PTC instruction from the processor's translation lookaside buffer. By purging the virtual address, the memory is deallocated.
REFERENCES:
patent: 4779188 (1988-10-01), Gum et al.
patent: 5437017 (1995-07-01), Moore et al.
patent: 5506953 (1996-04-01), Dao
patent: 5574878 (1996-11-01), Onodera et al.
patent: 5603056 (1997-02-01), Totani
patent: 5617537 (1997-04-01), Yamada
patent: 5644575 (1997-07-01), McDaniel
patent: 5682512 (1997-10-01), Tetrick
patent: 577429 (1998-07-01), Sukegawa et al
patent: 5784394 (1998-07-01), Alvarez et al.
patent: 5784706 (1998-07-01), Oberlin et al
patent: 5906001 (1999-05-01), Wu et al.
patent: 6128282 (2000-10-01), Liebetreu et al.
patent: 6339812 (2002-01-01), McCracken et al.
patent: 6374331 (2002-04-01), Janakiraman et al.
patent: 6412056 (2002-06-01), Gharachorloo et al
Gjessing, et al., “Performance of the RamLink Memory Archritecture”,Proceedings HICSS'94, (1994), 154-162.
Gjessing , Stein., et al., “RamLink: A High-BandwidthPoint-to-Point Memory Architecture”,Proceeding CompCon, (1992),328/331.
IEEE STD, “IEEE Standard for High-Bandwidth Memory Interface Based on Scalable Coherent Interface(SCI) Signaling Technology (RAMLink)”,IEEE Std 1596.4-1996, (1996), 1-91.
Peikari B. James
Silicon Graphics Inc.
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