Distributed write data drivers for burst access memories

Details Distributed write data drivers for burst access memories Distributed write data drivers for burst access memories

2008-07-08

2008-07-08

Nguyen, Viet Q (Department: 2827)

Static information storage and retrieval

Read/write circuit

Particular write circuit

C365S189050, C365S189080, C365S236000, C365S230060

Reexamination Certificate

active

11419166

ABSTRACT:
An address strobe latches a first address. A burst cycle increments the address internally with additional address strobes. A new memory address is only required at the beginning of each burst access. Read/Write commands are issued once per burst access eliminating toggling Read/Write control line at cycle frequency. Control line transition terminates access and initializes another burst access. Write cycle times are maximized thereby allowing increases in burst mode operating frequencies. Logic near sense amplifiers control write-data drivers thereby providing maximum write times without crossing current during I/O line equilibration. By gating global write-enable signals with global equilibrate signals locally at sense amps, local write-cycle control signals are provided and valid for essentially the entire cycle time minus an I/O line equilibration period in burst access memory. For nonburst mode, write begins following end of equilibration cycle to provide maximum write time without interfering with subsequent access-cycle address setup time.

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