Static information storage and retrieval – Read/write circuit – Including reference or bias voltage generator
Reexamination Certificate
2000-01-24
2001-04-03
Nelms, David (Department: 2818)
Static information storage and retrieval
Read/write circuit
Including reference or bias voltage generator
C365S196000
Reexamination Certificate
active
06212108
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates generally to semiconductor memory devices. More particularly, the present invention relates to reducing the time required to read data from a semiconductor memory integrated circuit.
In conventional designs for memory circuits, bit lines extend from the core cell array to permit the data stored in the individual core cells to be sensed by a sense amplifier. Select transistors are coupled between the bit lines and data lines. When a column of core cells on the bit line is selected by the address supplied to the memory device, the select transistors associated with that column are turned on, coupling the bit line and the data line. The selected core cell draws a current which is conveyed through the bit line, select transistor and data line to a sense amplifier which detects the state of the core cell.
In some memory devices, the bit lines and the data lines can have a heavy capacitive load. These lines cross many other lines of the circuit in the selection circuit and other circuits. In some designs, the data lines can be very long between the select transistors and the sense amplifiers, and may even be routed across the length of the integrated circuit containing the memory device. Because the current drawn by the core cell is small, on the order of a few microamps, and because the resistive-capacitive (RC) time constant of the bit line and data line can be large, the variation of the voltage on these lines due to the core cell current can be very slow.
It is desirable to speed up the voltage transition on the bit line and the data line to reduce the read access time of the memory. Faster memory access times are always preferred. The time required to sense the state of the selected core cell is a key component of the read access time. If this sensing time can be reduced, the performance of the entire memory device is improved.
It is known to improve the speed of some logic circuits by pre-charging a node to a predetermined voltage. When a voltage to be detected is subsequently applied, the pre-charging is released and the node voltage is driven to its active level. A sensing circuit such as an operational amplifier compares the active level with a threshold voltage and produces an output.
Pre-charging a data line or a bit line has had only a limited effect however, particularly in large memories. In a large integrated circuit, the capacitive loading on the data line and the bit line is so great that it even slows down the pre-charging operation. The pre-charging circuit typically cannot supply enough current to rapidly pre-charge a bit line or data line in a memory circuit.
Accordingly, there is a need in the art for a circuit and method which reduces the read access time of a semiconductor memory.
BRIEF SUMMARY OF THE INVENTION
By way of example only, a memory device in accordance with the present invention includes distributed bias circuits for charging the data lines or bit lines of a memory to an initial voltage. Several bias circuits are distributed along the length of the data line. This reduces the effect of the distributed capacitance of the data line. A control signal is provided to the bias circuits to initiate charging of the data line and to isolate the bias circuits from the data line when the associated bit line is selected for reading. In other embodiments, bias circuits are applied to the bit lines themselves to reduce the voltage transition time on those nodes.
The foregoing discussion of the preferred embodiments has been provided only by way of introduction. Nothing in this section should be taken as a limitation on the following claims, which define the scope of the invention.
REFERENCES:
patent: 4796230 (1989-01-01), Young
patent: 5132933 (1992-07-01), Schreck
patent: 5774395 (1998-06-01), Richart et al.
Akaogi Takao
Cleveland Lee Edward
Advanced Micro Devices , Inc.
Brinks Hofer Gilson & Lione
Le Thong
Nelms David
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