Distributed vector architecture

Details Distributed vector architecture Distributed vector architecture

1997-12-10

1999-08-31

Shah, Alpesh M.

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

395395, 711157, G06F 1576

Patent

active

059464968

ABSTRACT:
A vector/scalar computer system has nodes interconnected by an interconnect network. Each node includes a vector execution unit, a scalar execution unit, physical vector registers holding physical vector elements, a mapping vector register holding a mapping vector, and a memory. The physical vector registers from nodes together form an architectural vector register having architectural vector elements. The mapping vector defines an assignment of architectural vector elements to physical vector elements for its node. The memories from the nodes together form an aggregate memory.

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