Distributed VDC for SRAM memory

Static information storage and retrieval – Floating gate – Particular connection

Reexamination Certificate

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Details

C365S154000, C365S226000, C365S230030, C365S230060, C365S189090

Reexamination Certificate

active

08077517

ABSTRACT:
An integrated circuit structure includes a memory. The memory includes a first memory macro and a second memory macro identical to the first memory macro. A first power block is connected to the first memory macro and is configured to provide a regulated voltage to the first memory macro. The first power block has a first input and a first output. A second power block substantially identical to the first power block is connected to the second memory macro and is configured to provide the regulated voltage to the second memory macro. The second power block has a second input and a second output. The first input and the second input are interconnected. The first output and the second output are interconnected.

REFERENCES:
patent: 7679345 (2010-03-01), Verma et al.
patent: 7746047 (2010-06-01), Yin et al.
patent: 7764111 (2010-07-01), Chiu et al.
patent: 7768856 (2010-08-01), Fook et al.
patent: 2007/0121370 (2007-05-01), Ellis et al.
patent: 2008/0231240 (2008-09-01), Parkes et al.
patent: 1975926 (2007-06-01), None
Chen, Y.H., et al., “A 0.6V 45nm Adaptive Dual-rail SRAM Compiler Circuit Design for Lower VDD—min VLSIs,” 2008 Symposium on VLSI Circuits Digest of Technical Papers, 2 pgs., IEEE.

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