Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
Patent
1996-11-14
1999-07-06
Cabeca, John W.
Electrical computers and digital processing systems: memory
Storage accessing and control
Hierarchical memories
711145, 711141, G06F 1212
Patent
active
059208902
ABSTRACT:
A loop cache (26) is used in a data processing system for supplying instructions to a CPU to avoid accessing a main memory. Whether instructions stored in the loop cache can be supplied to the CPU is determined by a distributed TAG associated with the instruction address computed by the CPU. The instruction address includes an LCACHE index portion (42), an ITAG portion (44), and a GTAG (46). LCACHE index (42) selects corresponding locations in each of an ITAG array (50), an instruction array (52), and a valid bit array (54). A stored GTAG value (48) is chosen irrespective of where LCACHE index (42) is pointing. The GTAG portion of the instruction address (40) is compared to the stored GTAG value (48). The ITAG portion (44) of instruction address (40) is compared with the indexed ITAG of the ITAG array (50). If both the GTAG and ITAG compare favorably, the instruction is supplied from the loop cache to the CPU, rather than from main memory.
REFERENCES:
patent: 4763253 (1988-08-01), Bluhm et al.
patent: 5222224 (1993-06-01), Flynn et al.
patent: 5510934 (1996-04-01), Brennan et al.
patent: 5511178 (1996-04-01), Takeda et al.
J. Bunda, "Instruction Processing Optimization Techniques for VLSI Microprocessors," PhD thesis Deptartment of Computer Science, Univ. of Texas, Austin, Chapter 7, May, 1993, pp. 95-114.
Ramesh Panwar and David Rennels, "Reducing the frequency of tag compares for low power I-cache design," 1995 Intl. Symposium on Low Power Design, Dana Point, CA, Apr., 1995, pp. 57-62.
J. Thornton, Design of a Computer: CDC 6600 Scot Foresman, Publisher: Glenview IL, 1970, pp. 12-15, 110-141, 173-175.
Andra Seznec, "Decoupled Sectored Caches: conciliating low tag implementation cost and low miss ratio," Proc IEEE 21st Intl. Symposium on Computer Architecture, Jun. 1994, pp. 384 -392.
Ching-Long Su and Alvin M. Despain, "Cache Designs for Energy Efficiency," 28th Hawaii International Conf. on System Sciences, Jan. 1995.
Dake Liu and Christer Svensson, "Power Consumption Estimation in CMOS VLSI Chips," Journal of Solid State Circuits, vol. 29, No. 6, Jun. 1994, pp. 663-670,.
Ching-Long Su and Alvin M. Despain, "Cache Design Trade-offs for Power and Performance Optimization: A Case Study," 1995 Intl. Symp. Low Power Design, Dana Point, CA, pp. 63-68.
Kiyoo Itoh, Katsuro Sasaki, and Yoshinobu Nakagone, "Trends in Low-Power RAM Circuit Technologies," '94 Symp. on Low Electronics, San Diego, CA, Oct. 1994, pp. 84-87.
John Bunda, W. C. Athas and Don Fussell, "Evaluating Power Implications of CMOS Microprocessor Design Decisions," Intl Workshop on Low Power Design, Napa Valley, CA, Apr., 1994, pp.. 147-152.
Arends John
Lee Lea Hwang
Moyer William C.
Cabeca John W.
Goddard Patricia S.
Hill Daniel D.
Motorola Inc.
Peikari J.
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