Distributed table-driven power mode computation for...

Details Distributed table-driven power mode computation for... Distributed table-driven power mode computation for...

2008-12-31

2011-11-22

Stoynov, Stefan (Department: 2116)

Electrical computers and digital processing systems: support

Computer power control

Power conservation

C713S320000, C713S324000, C307S029000, C307S031000, C702S060000, C702S064000

Reexamination Certificate

active

08065542

ABSTRACT:
A method for computing the optimal power mode for a system-on-chip (SoC) in which both the clock and Vdd settings are controlled. Information from hardware blocks is synthesized into a global power mode for the entire SoC. The clocks can be disabled or enabled, and Vdd voltages can be disabled, set at a nominal operating level, and set at a retention level in which the state of memory and registers is retained.

REFERENCES:
patent: 6988211 (2006-01-01), Cline et al.
patent: 7178044 (2007-02-01), Pappalardo et al.
patent: 7206949 (2007-04-01), Kuranuki
patent: 7421601 (2008-09-01), Bose et al.
patent: 7500204 (2009-03-01), Pineda De Gyvez et al.
patent: 2008/0109656 (2008-05-01), Kotzin
patent: WO 2008/012483 (2008-01-01), None
ISA/EP, International Search Report dated Mar. 18, 2010 for International App. No. PCT/US2009/069829.

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