Distributed shared-memory packet switch

Multiplex communications – Pathfinding or routing – Switching a message which includes an address header

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370429, H04L 1254

Patent

active

061608149

ABSTRACT:
A packet switch (26) has N digital input ports (28) each of bandwidth B for receiving data cells including destination addresses for determining output ports, a shared input cache (32), N memory modules (36) of bandwidth N.times.B for buffering, a switch fabric (38), and N digital output ports (40). A digital multiplexer (30) receives each data cell from the input ports (28) and writes it to the shared input cache (32) together with a corresponding port queue number, queue position, and memory module number in response to its destination address so that (1) cells having the same queue number are cyclically assigned to different memory modules (36) and (2) cells having the same queue position are cyclically assigned to different memory modules (36). A digital demultiplexer (34) reads each data cell from the shared input cache (32) and writes it to one of the N memory modules (36) according to its assigned memory module number and queue position. Then the switch fabric (38) reads the data cells in each memory module (36) by queue position and writes each to a corresponding output port (40) matching the cell's queue number.

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Wei, et al., "Decentalized Control of a Multiple Shared Memory Module ATM Switch", IEEE, Supercomm/International Conference on Communications '92, pp. 704-708.
Wei, et al., "On the Mulitple Shared Memory Module Approach to ATM Switching", IEEE Infocom '92 The Conference on Computer Communications, vol. 1 of 3, '92, pp. 116-123.
Kondoh, et al., A Shared Multibuffer Architecture for High-Speed ATM Switch LSIs, IEICE Trans Electron., vol E76-C, No. 7, Jul. 1993, pp. 1094-1101.

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