Distributed random access memory in a programmable logic device

Details Distributed random access memory in a programmable logic device Distributed random access memory in a programmable logic device

2006-08-01

2006-08-01

Tran, Anh Q. (Department: 2819)

Electronic digital logic circuitry

Multifunctional or programmable

Having details of setting or programming of interconnections...

C326S040000, C326S046000

Reexamination Certificate

active

07084665

ABSTRACT:
Distributed random access memory in a programmable logic device uses configuration RAM bits as bits of the distributed RAM. A single write path is used to provide both configuration data and user write data. Selection circuitry, such as a multiplexer, is used to determine whether the single write path carries configuration data or user write data. In another aspect of the invention, the configuration RAM bits are used as to construct a shift register by adding pass transistors to chain the configuration RAM bits together, and clocking alternate pass transistors with two clocks 180° out of phase with one another.

REFERENCES:
patent: 5343406 (1994-08-01), Freeman et al.
patent: 5352940 (1994-10-01), Watson
patent: 5414377 (1995-05-01), Freidin
patent: 5432719 (1995-07-01), Freeman et al.
patent: 5550782 (1996-08-01), Cliff et al.
patent: 5566123 (1996-10-01), Freidin et al.
patent: 5572148 (1996-11-01), Lytle et al.
patent: 5648732 (1997-07-01), Duncan
patent: 5796269 (1998-08-01), New
patent: 5889413 (1999-03-01), Bauer
patent: 6029236 (2000-02-01), Steele et al.
patent: 6128215 (2000-10-01), Lee
patent: 6208163 (2001-03-01), Wittig et al.
patent: 6215326 (2001-04-01), Jefferson et al.
patent: 6249143 (2001-06-01), Zaveri et al.
patent: 6356110 (2002-03-01), Reddy et al.
patent: 6411124 (2002-06-01), Lee et al.
patent: 6462577 (2002-10-01), Lee et al.
P. Chow et al., “A 1.2μm CMOS FPGA using Cascaded Logic Blocks and Segmented Routing”,FPGAs, Chapter 3.2, pp. 91-102, W.R. Moore and W. Luk (eds.), Abingdon EE&CS Books, Abingdon (UK) 1991, no month.
L. Mintzer, “FIR Filters with the Xilinx FPGA”, FPGA '92 #129-#134, no month.
“Optimized Reconfigurable Cell Array (ORCA) Series Field-Programmable Gate Arrays”, Advance Data Sheet, AT&T Microelectronics, Feb. 1993, pp. 1-36 and 65-87.
The Programmable Logic Data Book, 1994, Xilinx, Inc., San Jose, CA, cover pages and pp. 2-5 through 2-102 (“XC4000 Logic Cell Array Families”), no month.
B. Klein, “Use LFSRs to Build FPGA-Based Counters”,Electronic Design, Mar. 21, 1994, pp. 87, 88, 90, 94, 97 and 100.
A. DeHon, “Reconfigurable Architectures for General-Purpose Computing”, M.I.T. Ph.D. thesis, Sep. 1996.
R. Iwanczuk, “Using the XC4000 RAM Capability”, XAPP 031.000, Xilinx, Inc., San Jose, CA, no month.
J.R. Hauser et al., “Garp: A Mips Processor with a Reconfigurable Coprocessor”, 0-8186-8159-4/97 $10.00 © 1997 IEEE, pp. 21-21, no month.
A. Ohta et al., “New FPGA Architecture for Bit-Serial Pipeline Datapath”, 0-8186-8900-5/98 $10.00 © 1998 IEEE, pp. 58-67, no month.
“XC4000E and XC4000X Series Field Programmable Gate Arrays: Product Specification”, May 14, 1999 (Version 1.6), Xilinx, Inc., San Jose, CA, pp. 6-5 through 6-72.
“Flex 10K Embedded Programmable Logic Family”, Data Sheet, Jun. 1999, ver. 4.01, Alter Corporation, San Jose, CA, pp. 1-137.
“Flex 10K Embedded Programmable Logic Family”, Data Sheet, Aug. 1999, ver. 2.02, Altera Corporation, San Jose, CA, pp. 1-120.
“XC4000XLA/XV Field Programmable Gate Arrays: Product Specification”, DS015 (v1.3) Oct. 18, 1999, Xilinx, Inc., San Jose, CA, pp. 6-157 through 6-170.
“Triscend E5 Configurable System-on-Chip Family”, Triscend Corporation, Jan. 2000 (Version 1.00) Product Description, cover page and pp. 25-28.
“Apex 20K Programmable Logic Device Family”, Data Sheet, Mar. 2000, ver. 2.06, Altera Corporation, San Jose, CA, pp. 1-208.
“Virtex 2.5V Field Programmable Gate Arrays”, DS003 (v.2.0), Preliminary Product Specification, Mar. 9, 2000, Xilinx, Inc., San Jose, CA, pp. 1-72.
“Virtex-E 1.8V Extended Memory Field Programmable Gate Arrays”, DS025 (v1.0) Mar. 23, 2000, Advance Product Specification, Xilinx, Inc., San Jose, CA, pp. 1 and 6.

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