Distributed processor memory module and method

Details Distributed processor memory module and method Distributed processor memory module and method

2000-08-31

2004-08-31

Kim, Matthew (Department: 2186)

Electrical computers and digital processing systems: memory

Storage accessing and control

Shared memory area

C711S005000

Reexamination Certificate

active

06785780

ABSTRACT:

TECHNICAL FIELD
This invention relates to memory devices, and more particularly to memory modules having on-board processors.
BACKGROUND OF THE INVENTION
A conventional computer system
10
shown in
FIG. 1
includes a central processing unit (“CPU”)
12
, such as a microprocessor, that is coupled to a bus bridge
16
, memory controller or the like. The CPU
12
is also typically coupled to a cache memory
18
to allow instructions and data to be more frequently accessed by the CPU
12
. The bus bridge
16
allows the CPU
12
to receive program instructions from a system memory
20
. The CPU
12
can also write data to and read data from the system memory
20
through the bus bridge
16
. The CPU
12
also preferably transfers video data from the system memory
20
to a display system including a graphics processor or graphics accelerator
24
, a video RAM
26
, and a conventional display
28
, such as a cathode ray tube (“CRT”), liquid crystal display (“LCD”) or field emission display (“FED”). The graphics accelerator
24
processes graphics data to free up the CPU
12
from performing that function. The graphics accelerator
24
writes video data to and reads video data from the video RAM
26
, and generates a video signal that is applied to the display
28
. The bus bridge
16
also interfaces the CPU
12
to a peripheral bus
30
, such as a peripheral component interconnect (“PCI”) bus. The peripheral bus
30
is, in turn, coupled to at least one mass storage device, such as a disk drive
32
and a CD ROM drive
34
, and at least one user interface device, such as a keyboard
36
and a pointing device
38
. The computer system
10
may, of course, contain a greater or lesser number of components.
As shown in
FIG. 2
, the system memory
20
is generally in the form of several integrated circuit memory devices
40
, such as dynamic random access memories (“DRAMs”) and which may be Advanced Technology (“AT”) Drams, such as RAMBUS DRAMs (“RDRAMs”) or synchronous link DRAMs (“SLDRAMs”), mounted on a printed circuit board
42
. The resulting memory module
44
is then removably plugged into a mother-board
46
of a computer system
10
(FIG.
1
). The size of the computer system's memory can be increased by simply plugging additional memory modules
44
into the mother-board
46
. Memory modules
44
are commercially available in standardized configurations, such as a single in-line memory module (“SIMM”) and a double in-line memory module (“DIMM”). The memory modules
44
are electrically coupled to a memory controller
50
or other device (not shown) mounted on the mother-board
46
using standardized memory interfaces. These standardized memory interfaces generally include a data bus, an address bus, and a control/status bus.
Transferring data and instructions to and from the system memory
20
is a frequent event, and it can consume a substantial percentage of the available processing time of the CPU
12
. To reduce the processing burden on the CPU
12
, direct memory access procedures may be employed in which data and instructions are transferred to and from the system memory
20
by device other than the CPU
12
. For example, instructions may be transferred directly from a basic input-output system (“BIOS”) read only memory (“ROM”) (not shown) or from a disk drive
32
(
FIG. 1
) for subsequent reading and execution by the CPU
12
. Graphics data stored in the system memory
20
may be transferred directly to the graphics accelerator
24
without the use of the CPU
12
. Direct memory accesses thus allow the CPU
12
to perform other functions during accesses to the system memory
20
. Direct memory access may similarly be used to transfer data to and from the video RAM
26
without using the CPU
12
.
Although direct memory access procedures can free-up the CPU
12
to perform other functions during a simple data transfer procedure, there are other memory intensive processing functions occurring in the computer system
10
that cannot be performed easily by devices other than the CPU
12
. For example, “data mining” is a procedure by which data stored in the system memory
20
is searched for the presence of predetermined patterns or values of characters. A data mining algorithm causes the CPU
12
to repetitively read data from the system memory
20
and compare the read data to the predetermined data. Since this procedure requires that data not only be transferred from the system memory
20
but also be compared to the predetermined data, the CPU
12
is normally required to perform this procedure. The processing power of the CPU
12
is also required to execute a wide variety of other memory intensive algorithms, such as speech recognition algorithms.
Attempts have been made to free CPUs from executing memory intensive algorithms by placing dedicated processors on memory modules, such as the memory module
44
shown in FIG.
2
. An example of a conventional memory module containing on-board processing capability is shown in FIG.
3
. The memory module
60
includes several memory devices
62
, such as DRAMs, mounted on a printed circuit substrate
64
. The module
60
also includes a respective dedicated processor
70
coupled to each memory device
62
though a bus system
72
. A single program memory
74
receives and then stores instructions coupled from appropriate circuitry (not shown) on the mother-board
46
FIG. 2
) through a program bus
76
. The program memory
74
supplies the stored instructions to all of the processors
70
. Generally the same or related instructions are supplied to all of the processors
70
so that the processors
70
operate in parallel. The processor
70
is generally a reduced instruction set computer (“RISC”), although more conventional processors may also be used.
In operation, prior to performing a memory intensive function, the module
60
is programmed by supplying the program memory
74
through the program bus
76
with instructions to perform a predetermined algorithm. The processors
70
then fetch the instructions stored in the program memory
74
, and perform the corresponding functions. These functions will normally include reading data from the memory devices
62
and writing data to the memory devices
62
. Significantly, the CPU
12
of the computer system
10
need not be involved in performing these functions, although the CPU
12
may be involved in initially providing the instructions to the program memory
74
. As a result, the CPU
12
is free to perform other functions during these memory intensive operations. The memory module
60
, may, of course, be used as a conventional memory module, in which case it interfaces with the mother-board
46
through a conventional bus system
80
including a data bus, address bus, and control/status bus. The bus system
80
, as well as the program bus
76
, generally interface with the mother-board
46
through an edge connector
88
a,b.
The memory module
60
shown in
FIG. 3
can be effective in greatly improving the processing power of computer systems
10
performing memory intensive algorithms. Its primary limitation is the requirement that the mother-board
46
be specially adapted to interface with the memory module
60
. More specifically, the mother-board
46
must include a bus for interfacing with the program bus
76
, as well as appropriate circuitry for supplying the instructions to the bus
76
. Different memory modules
60
may, of course, use different processors
70
, thereby requiring that the instruction set provided by the mother-board
46
be matched to the processor
70
. Additionally, the edge connector
88
is inherently different from a conventional memory a module edge connector because it must include terminals for the processor bus
76
. Computer systems
10
, and hence mother-boards
46
, are available from a wide variety of manufacturers, and so are memory modules. As a result, conventional memory modules
60
that include on-board processors
70
must be specially matched to specific computer systems
10
, thus making the use of such memo

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