Error detection/correction and fault detection/recovery – Data processing system error or fault handling – Reliability and availability
Reexamination Certificate
2000-06-29
2004-07-27
Beausoliel, Robert (Department: 2184)
Error detection/correction and fault detection/recovery
Data processing system error or fault handling
Reliability and availability
C714S031000
Reexamination Certificate
active
06769072
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a distributed-processing equipment having a processor that reconfigures redundant devices in accordance with their operating states and one or a plurality of processors that operate in link with those devices.
2. Description of the Related Art
In recent years, in many facilities such as exchanges that should operate continuously, functional distribution and load distribution are made by combining inexpensive microprocessors and high-level information processing technologies in an organic manner. Further, those facilities are configured as a distributed processing system which enables improvements in processing efficiency, response speed, reliability, and availability as well as can flexibly adapt to a sudden load variation and system expansion.
The hardware and software of such a facility is standardized in accordance with the forms of functional distribution and load distribution and are configured as a set of a variety of packages (modules) that conform to the standardization.
Each module employs a redundant structure that depends on the degree of influence of a failure or a fault occurring therein on other modules. If recovery from an actual failure or fault cannot be made by error correction or retrial, the module is reconfigured.
FIG. 12
shows an example of an exchange that is configured as a distributed processing system.
In
FIG. 12
, duplicated main processors (MPR)
40
-
1
and
40
-
2
, duplicated call processors (CPR)
41
-
11
to
41
-
1
N, and
41
-
21
to
41
-
2
N that are provided according to a load distribution scheme, and duplicated signaling/path processors (SPP)
42
-
1
and
42
-
2
are connected to duplicated ATM links
43
-
1
and
43
-
2
via two sets of communication ports, respectively. The main processors
40
-
1
and
40
-
2
are connected to duplicated monitoring processors (ADM)
44
-
1
and
44
-
2
via duplicated communication links, and connected to one or a plurality of workstations (WS)
46
-
1
to
46
-n and a printer
47
via a LAN
45
to which a CSMA/CD scheme is applied. The signaling/path processors
42
-
1
and
42
-
2
are connected to duplicated signaling/path controllers (LRPC)
48
-
1
and
48
-
2
via duplicated communication links, and particular communication ports of the signaling/path controllers (LRPC)
48
-
1
and
48
-
2
are connected to communication ports of duplicated switches (MSCSH)
49
-
1
and
49
-
2
, respectively.
First ports of the ports of the switches
49
-
1
and
49
-
2
are connected to duplicated signaling multiplexing sections (SGCMDX)
50
-
1
and
50
-
2
, respectively. Signaling controllers (SGC)
51
-
1
and
51
-
2
are connected to the signaling multiplexing sections
50
-
1
and
50
-
2
via duplicated links, respectively. Two communication ports of the respective signaling controllers
51
-
1
and
51
-
2
are connected to particular communication ports of the call processors
41
-
11
to
41
-
1
N and
41
-
21
to
41
-
2
N and the signaling/path processors
42
-
1
and
42
-
2
via duplicated communication links.
Second ports of the switches
49
-
1
and
49
-
2
are connected to digital terminal shelves (DTC)
53
-
1
and
53
-
2
that are mounted with a desired number p of digital terminals (DT)
52
-
1
to
52
-p.
Third ports of the switches
49
-
1
and
49
-
2
are connected to line trunk shelves (LTC)
59
-
1
and
59
-
2
that are mounted, in a predetermined number and combination, with a line circuit (SLC)
54
that is connected to a subscriber line, a digital line circuit (DLC)
55
that is connected to a digital subscriber line, a switch-board interfacing part (AT)
56
that is connected to a switch-board (not shown), a service trunk (SVT)
57
, and a register (REC)
58
.
In the exchange having the above configuration, at a start or after reconfiguration (mentioned above), the signaling/path controllers
48
-
1
and
48
-
2
give predetermined instructions to the switches
49
-
1
and
49
-
2
, whereby communication links (hereinafter referred to as “fixed communication links”) are formed as fixed speech paths in the switches
49
-
1
and
49
-
2
so as to establish mesh-like connections between the signaling/path processors
42
-
1
and
42
-
2
and the signaling multiplexing sections
50
-
1
and
50
-
2
, the digital terminal shelves
53
-
1
and
53
-
2
, and the line trunk shelves
59
-
1
and
59
-
2
.
The main processors
40
-
1
and
40
-
2
, the call processors
41
-
11
to
41
-
1
N and
41
-
21
to
41
-
2
N, and the signaling/path processors
42
-
1
and
42
-
2
are connected to each other via netty channels that are formed as PVCs in the ATM links
43
-
1
and
43
-
2
.
The signaling/path processors
42
-
1
and
42
-
2
are loose-coupled with the main processors
40
-
1
and
40
-
2
and the call processors
41
-
11
to
41
-
1
N and
41
-
21
to
41
-
2
N, via the above-mentioned fixed communication links and channels, to monitor the operating states of the duplicated monitoring processors
44
-
1
and
44
-
2
, signaling/path controllers
48
-
1
and
48
-
2
, switches
49
-
1
and
49
-
2
, signaling multiplexing sections
50
-
1
and
50
-
2
, signaling controllers
51
-
1
and
51
-
2
, digital terminal shelves
53
-
1
and
53
-
2
, and line trunk shelves
59
-
1
and
59
-
2
.
When necessary, the signaling/path processors
42
-
1
and
42
-
2
dynamically reconfigure the above devices by supplying them with instructions that conform to results of the monitoring via the above-mentioned fixed communication links and channels.
Therefore, the main processors
40
-
1
and
40
-
2
, the call processors
41
-
11
to
41
-
1
N and
41
-
21
to
41
-
2
N, the monitoring processors
44
-
1
and
44
-
2
, the signaling/path controllers
48
-
1
and
48
-
2
, the switches
49
-
1
and
49
-
2
, the signaling multiplexing sections
50
-
1
and
50
-
2
, the signaling controllers
51
-
1
and
51
-
2
, the digital terminal shelves
53
-
1
and
53
-
2
, and the line trunk shelves
59
-
1
and
59
-
2
operate with the above-mentioned duplication-type redundant structure and thereby maintain high functionality and performance of the exchange system.
The call processors
41
-
11
to
41
-
1
N and
41
-
21
to
41
-
2
N perform call processing according to a load distribution scheme.
During the course of this call processing, when necessary, the signaling/path processors
42
-
1
and
42
-
2
and the signaling/path controllers
48
-
1
and
48
-
2
relay and distribute messages to be passed to or from:
the call processors
41
-
11
to
41
-
1
N and
41
-
21
to
41
-
2
N; or
the switches
49
-
1
and
49
-
2
, the signaling controllers
51
-
1
and
51
-
2
, the digital terminal shelves
53
-
1
and
53
-
2
, the line trunk shelves
59
-
1
and
59
-
2
, the digital terminals
52
-
1
to
52
-p, the line circuit
54
, the digital line circuit
55
, the switch-board interfacing part
56
, the service trunk
57
, and the register
58
.
The main processors
40
-
1
and
40
-
2
collect information to be used for maintenance and operation of the individual sections by exchanging predetermined messages via the above-mentioned channels and fixed communication links.
The monitoring processors
44
-
1
and
44
-
2
perform man-machine interface relating to the maintenance and operation and support the maintenance and operation by cooperating, when necessary, with the workstations
46
-
1
to
46
-n and the printer
47
that are connected to the main processors
40
-
1
and
40
-
2
via the LAN
45
.
Processing to be performed in each section to realize the above-mentioned call processing, maintenance, and operation is not a characterizing feature of the invention and can be realized by using a variety of known techniques, and hence will not be described here.
Incidentally, among the above duplicated modules (packages), the signaling controllers
51
-
1
and
51
-
2
, for example, exchange, via the above-mentioned channels and fixed communication links, predetermined register signals with one of the c
Kawamura Kengo
Kishida Takayuki
Beausoliel Robert
Chu Gabriel
Katten Muchin Zavis & Rosenman
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