Distributed processing in a cryptography acceleration chip

Details Distributed processing in a cryptography acceleration chip Distributed processing in a cryptography acceleration chip

2000-07-06

2009-10-06

Rones, Charles (Department: 2164)

Electrical computers and digital processing systems: support

Data processing protection using cryptography

Having separate add-on board

C713S153000, C370S389000

Reexamination Certificate

active

07600131

ABSTRACT:
Provided is an architecture for a cryptography accelerator chip that allows significant performance improvements over previous prior art designs. In various embodiments, the architecture enables parallel processing of packets through a plurality of cryptography engines and includes a classification engine configured to efficiently process encryption/decryption of data packets. Cryptography acceleration chips in accordance may be incorporated on network line cards or service modules and used in applications as diverse as connecting a single computer to a WAN, to large corporate networks, to networks servicing wide geographic areas (e.g., cities). The present invention provides improved performance over the prior art designs, with much reduced local memory requirements, in some cases requiring no additional external memory. In some embodiments, the present invention enables sustained full duplex Gigabit rate security processing of IPSec protocol data packets.

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