Distributed placement, variable-size cache architecture

Details Distributed placement, variable-size cache architecture Distributed placement, variable-size cache architecture

1993-04-30

1998-07-07

Swann, Tod R.

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

364DIG1, 364DIG2, 3642434, 36424341, 711117, 711128, 711154, G06F 1200

Patent

active

057784248

ABSTRACT:
A distributed variable-size cache placement architecture includes plural cache storage units (CSUs), each of which includes a CSU control logic, an address director, a data director, a placement array, placement logic (i.e., distribution controller), and a set associative memory for caching data. All CSUs in the architecture are connected over a communication network to a single processor interface and mainstore and which provides information to all CSUs about the status of each of the other CSUs. Any number of CSUs may be connected in parallel to provide a variable size cache. All CSUs sharing a processor interface utilize the same placement block size, contain the same number of sets of cache elements and use the same CSU placement mechanism.

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