Distributed NOR tag match apparatus

Details Distributed NOR tag match apparatus Distributed NOR tag match apparatus

1993-08-31

1996-11-05

Dinh, Son T.

Static information storage and retrieval

Associative memories

Ferroelectric cell

36518907, 36518911, 395427, G11C 1504

Patent

active

055724566

ABSTRACT:
A system for providing a CMOS NOR function that is distributed across a number of devices located on different chips. Specifically the present invention may be implemented in tag RAMs to provide expanded addressing. In other words, larger addresses may be processed using the present invention. This function is provided by using some transistors on each chip as part of the CMOS NOR gate. The tag RAM includes: a first input for receiving a first portion of an address, a second input for receiving a second portion of the address; a memory array connected to the first input; a comparator connected to the memory array and the second input, wherein the comparator has an output that produces an output signal in response to receiving a first signal from the second input and a second signal from the memory array; a first transistor having a gate connected to the output of the comparator, a first source/drain connected to a first pin, and a second source/drain connected to a second pin; and a second transistor having a gate connected to the output of the comparator, a first source/drain connected to the output pin, a second source/drain connected to a lower power supply voltage source.

REFERENCES:
patent: 5031141 (1991-07-01), Guddat et al.
patent: 5146428 (1992-09-01), Tanimura
patent: 5218567 (1993-06-01), Suzuki et al.
patent: 5319348 (1994-06-01), Lee et al.

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