Electrical computers and digital processing systems: memory – Storage accessing and control – Control technique
Patent
1997-08-25
2000-04-25
Chan, Eddie P.
Electrical computers and digital processing systems: memory
Storage accessing and control
Control technique
711147, 711207, 711205, 711210, 711141, 711168, G06F 1200
Patent
active
060556102
ABSTRACT:
A distributed-memory multiprocessor system uses fast and main coherency directories to implement cache coherency. The main directory is stored with user data in main memory and includes sufficient information to determine which memory cells have cached copies of user data stored in main memory. In addition, the main directories specify the states of the cached data. The fast directories cache only some of the main-directory information for only a fraction of the main-memory locations at any given time. The fast directories are tagless in one mode and use partial tags in another mode. The fast-directory information is accessed concurrently with main-directory information in response to data requests. Directory information is retrieved first from the fast directory and is used to launch predictive recalls. Subsequently received main-directory information is used to validate or invalidate the predictive recalls. If invalidated, determined recalls are issued, and memory access times are the same as they would have been without the fast directory. If validated, the predictive recalls reduce data access times. To the extent that the predictive recalls are successful, overall system performance is improved.
REFERENCES:
patent: 5809539 (1996-12-01), Young et al.
patent: 5813030 (1997-05-01), Tubbs
patent: 5848434 (1996-12-01), Young et al.
patent: 5893142 (1996-11-01), Moyer et al.
Iacobovici Sorin
Smith Kenneth K.
Staley Loren P.
Chan Eddie P.
Hewlett--Packard Company
McLean Kimberly N.
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