Distributed memory module cache writeback

Details Distributed memory module cache writeback Distributed memory module cache writeback

2008-06-17

2008-06-17

Shah, Sanjiv (Department: 2185)

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

C711S005000, C711S100000, C711S128000, C711S135000, C711S147000, C711S148000

Reexamination Certificate

active

07389387

ABSTRACT:
One embodiment of a distributed memory module cache includes tag memory and associated logic implemented at the memory controller end of a memory channel. The memory controller is coupled to at least one memory module by way of a point-to-point interface. The data cache and associated logic are located in one or more buffer components on each of the memory modules. Writes to a memory module are stored in the data cache which allows the writes to be postponed until the DRAM on the memory module is not busy.

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