Distributed memory module cache prefetch

Details Distributed memory module cache prefetch Distributed memory module cache prefetch

2005-08-02

2005-08-02

Anderson, Matthew D. (Department: 2189)

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

C711S118000, C711S128000, C711S135000, C711S136000, C711S167000, C711S168000, C711S169000

Reexamination Certificate

active

06925534

ABSTRACT:
One embodiment of a distributed memory module cache includes tag memory and associated logic implemented at the memory controller end of a memory channel. The memory controller is coupled to at least one memory module by way of a point-to-point interface. The data cache and associated logic are located in one or more buffer components on each of the memory modules. One intended advantage of this example embodiment is the ability to read a current line of data out of a memory module DRAM and to load the next cache line of data into the memory module data cache. This allows the utilization of excess DRAM interconnect bandwidth while preserving limited memory bus bandwidth.

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