Distributed memory in field-programmable gate array...

Details Distributed memory in field-programmable gate array... Distributed memory in field-programmable gate array...

2008-05-30

2010-02-02

Chang, Daniel D (Department: 2819)

Electronic digital logic circuitry

Multifunctional or programmable

Array

C326S041000, C326S046000, C326S047000

Reexamination Certificate

active

07656191

ABSTRACT:
Circuitry for facilitating the use of the memory elements in the look-up tables (“LUTs”) of a field programmable gate array (“FPGA”) as user-accessible, distributed RAM. For example, a register associated with a LUT and that is not needed in the read data path in user RAM mode can be used to register data for writing in user RAM mode. As another example, an otherwise unneeded register associated with a LUT can be used to provide a synchronous read address signal for user RAM mode. Several other features are shown for similarly facilitating user RAM mode with minimal (if any) additional circuitry being required in the FPGA.

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