Electrical computers and digital processing systems: memory – Address formation – Address mapping
Reexamination Certificate
2002-01-22
2004-01-06
Sparks, Donald (Department: 2188)
Electrical computers and digital processing systems: memory
Address formation
Address mapping
Reexamination Certificate
active
06675281
ABSTRACT:
BACKGROUND OF THE INVENTION
(1) Field of the Invention
The invention relates to the fabrication of integrated circuit devices, and more particularly, to a method of rapidly updating the content of an arbitrarily selected flash memory cell and evenly spreading out the erasing of the blocks of data.
(2) Description of the Prior Art
Some of the well known characteristics of flash memory design and application can be highlighted as the following:
durability
have a small form factor
have a short access time, and
consume lower power.
For comparative purposes, the following characteristics as they apply to hard disk can be identified:
large storage capacity
are economical, and
have no limit on erase capabilities.
Flash memory is presently being used for mass storage, the above indicated characteristics highlight that there are a number of obvious advantages of the flash memory when compared with hard disk data storage, such as durability, having a small form factor, having short access time and relatively low power consumption. As disadvantages of the flash memory must be cited low storage capacity (presently available up to 1 Giga-byte which must be compared with 30 Giga-byte for a hard disk) while the flash memory is also more costly to create when compare with disk storage devices. One notable difference between the flash memory and disk storage is that flash memory is limited in its erasing capability, a drawback that does not exist for disk storage devices.
The problems with flash memory data are:
the flash memory must be erased before write
long erase time is required
the erase is bounded by a limited number of times that the erase operation can be performed, typically between 100,000 and 1,000,000 times.
An effective system design is required that addresses the above stated issues of flash memory implementation. For this and other reasons, a mass storage system that uses flash memory must have the following design features:
dynamic mapping of logical and physical addresses must be provided, and
a wear-level algorithm must be part of the design.
The system must be provided with a dynamic mapping table of logical and physical addresses so that the data does not need to be frequently erased. In addition, an algorithm must be provided that assures even wear of the memory cells, such that the entire memory does not become inoperative due to a portion of the memory reaching the end of life of the memory.
The conventional organization of a flash memory is highlighted in
FIG. 3
, which shows that:
a flash memory is divided in to blocks or cylinders, a block forms a unit of erasure
a block of a flash memory consists of pages or sectors, typically up to 16 pages, a page forms a unit of read/write, and
each of the pages of the flash memory contains 16 bytes of header information and 512 bytes of data.
One of the conventional methods that is applied to update data in flash memory follows the steps of:
copy data from a block to a buffer
update the data in the buffer with new data
erase data in the original block, and
copy the updated data from the buffer back to the block.
The conventional method of erasing one block of data at the time present problems for a conventional flash memory. If for instance only one byte of data needs to be changed in the flash memory, the data that is contained in the block (that comprises this byte) must be copied to a buffer, the buffer must then be updated, then the old data must be erased in the original block and finally a copy of the new data must be copied from the buffer to the block since erasing a block of data is a relatively time consuming operation, most systems will not approach data update operations in this manner.
Another conventional method that is applied to update data in flash memory follows the steps of:
copy data from a block to a buffer
update the data in the buffer with new data
find an empty block, this empty block is identified by a physical address
copy the updated data from the buffer back to the block, and
record or update the physical address of the located empty block in a corresponding mapping table.
The advantages of this latter method are:
eliminating of frequent erasing of data
saving of the long erase time, and
evening out of the wear-level of the data blocks.
The need however remains for an additional mapping table. Such a mapping table can be created as follows:
Logical address
Physical address
0
0
1
1
2
1000
3
3
4
1001
The above highlighted mapping table provides and maintains a one-to-one correspondence between logical data addresses and the physical addresses where the data resides on a data storage medium.
The conventional methods that are applied for the storage of a mapping table comprises one of the following:
stored on the SRAM in the controller
stored on the Content Addressable Memory (CAM) in the controller, and
stored in flash memory external to the controller.
The problems that are encountered with the first two of the above highlighted methods is that, if power is lost to the flash memory, all the data that is contained in the mapping table is lost. In addition, storing the mapping table in a specific place in a flash memory encounters the conventional problem of flash memory wear or endurance. The invention provides a method whereby the mapping table is stored in any location of the flash memory.
U.S. Pat. No. 6,230,233 (Lofgren et al.) discloses a mass storage system made of flash EEPROM cells. The relative usage of memory banks is monitored, and physical addresses are periodically changed to even-out flash cell wear.
U.S. Pat. No. 6,000,006 (Bruce et al.) describes a flash memory-based mass storage system. The physical address map is maintained in RAM. Wear leveling is performed.
U.S. Pat. No. 5,742,934 (Shinohara) teaches a flash memory-based hard disk. An address conversion table that depends on logical and physical sector numbers is used to extend the memory life.
U.S. Pat. No. 5,740,396 (Mason) describes a solid state disk comprising a flash memory. An address conversion method is used to convert the logical address to the physical address.
SUMMARY OF THE INVENTION
A main objective of the invention is to improve the procedure that is used to update data contained in the flash memory cell.
Another objective of the invention is to spread the erasing of data from a flash memory cell over the sequence of blocks that is being erased.
In accordance with the objectives of the invention a new algorithm is provided for the updating and erasing of flash memory data. The new algorithm effects and improves the write, the update and the read operations of the flash memory cell.
REFERENCES:
patent: 4577274 (1986-03-01), Ho et al.
patent: 5734816 (1998-03-01), Niijima et al.
patent: 5740396 (1998-04-01), Mason
patent: 5742934 (1998-04-01), Shinohara
patent: 6000006 (1999-12-01), Bruce et al.
patent: 6230233 (2001-05-01), Lofgren et al.
Oh Yaw
Tuan Jen Chieh
Ackerman Stephen B.
iCreate Technologies Corporation
Namazi Mehdi
Saile George O.
Sparks Donald
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