Distributed independent cache memory

Details Distributed independent cache memory Distributed independent cache memory

2007-11-06

2007-11-06

Peugh, Brian R. (Department: 2187)

Electrical computers and digital processing systems: memory

Address formation

Address mapping

C711S211000

Reexamination Certificate

active

10620249

ABSTRACT:
A system for transferring data to and from one or more slow-access-time-mass-storage nodes which store data at respective first ranges of logical block addresses (LBAs), including a plurality of interim-fast-access-time nodes which are configured to operate independently of one another. Each interim-fast-access-time node is assigned a respective second range of the LBAs and is coupled to receive data from and provide data to the one or more slow-access-time-mass-storage nodes within the respective second range.The system further includes one or more interface nodes, which are adapted to receive input/output (IO) requests from host processors directed to specified LBAs and to direct all the IO requests to the interim-fast-access-time node to which the specified LBAs are assigned.

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European Search Report dated Jan. 8, 2007, from corresponding European Application 04254198.7-1238.

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