Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2006-08-25
2009-02-24
Do, Thuan (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000, C716S030000, C716S030000, C430S005000, C430S030000
Reexamination Certificate
active
07496884
ABSTRACT:
A system that verifies a simulated wafer image against an intended design. During operation, the system receives a design. Next, the system generates a skeleton from the design, wherein the skeleton specifies cell placements and associated bounding boxes for the cell placements, but does not include geometries for the cell placements. The system then computes environments for cell placements based on the skeleton. Next, the system generates templates for cell placements, wherein a template for a cell placement specifies the cell placement and the environment surrounding the cell placement. The system then generates the simulated wafer image by performing model-based simulations for cell placements associated with unique templates.
REFERENCES:
patent: 2006/0143589 (2006-06-01), Horng et al.
Fang Weiping
Tang Zongwu
Wang Yibing
Zhang Huijuan
Do Thuan
Doan Nghia M
Park Vaughan & Fleming LLP
Synopsys Inc.
LandOfFree
Distributed hierarchical partitioning framework for... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Distributed hierarchical partitioning framework for..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Distributed hierarchical partitioning framework for... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-4087977