Distributed gated clock driver

Details Distributed gated clock driver Distributed gated clock driver

1997-01-29

1999-04-06

Tokar, Michael

Electronic digital logic circuitry

Clocking or synchronizing of logic stages or gates

Field-effect transistor

326 93, 327297, H03K 19096

Patent

active

058923730

ABSTRACT:
A gated clock driver is configured to provide an enable signal and a gated clock signal at each of a plurality flip-flops. One of the p-channel transistors of the gated clock driver's NOR gate is distributed to each of the flip-flops or latches in the system. Additionally, an extra n-channel transistor is provided in the gated clock circuit to form an inverter with the nondistributed p-channel transistor. More particularly, the p-channel transistor that is driven by the system clock input is distributed to each of the flip-flops. Similarly, the enable input (at the output of the new inverter) is distributed to each of the flip-flops. Since the gated clock signal cannot be generated without the enable signal being high and the system clock being low, distributing enable and the p-channel transistor which receives the system clock as an input minimizes clock skew as compared to flip-flops with a completely shared clock gating clock.

REFERENCES:
patent: 5008563 (1991-04-01), Kenny et al.
patent: 5013942 (1991-05-01), Nishimura et al.
patent: 5453707 (1995-09-01), Hiratsuka et al.
patent: 5670899 (1997-09-01), Kohdaka
patent: 5705942 (1998-01-01), Ashuri
patent: 5760609 (1998-06-01), Sharpe-Geisler
patent: 5760610 (1998-06-01), Naffziger

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