Distributed front-end FIFO for source-synchronous interfaces...

Details Distributed front-end FIFO for source-synchronous interfaces... Distributed front-end FIFO for source-synchronous interfaces...

2009-08-10

2010-10-05

Dinh, Son (Department: 2824)

Static information storage and retrieval

Read/write circuit

Serial read/write

C365S233100

Reexamination Certificate

active

07808855

ABSTRACT:
In one embodiment, an integrated circuit such as an FPGA includes one or more data I/O blocks, one or more FIFOs, and a FIFO controller. At least one data I/O block receives an incoming bit stream from an external device. At least one FIFO is connected to receive a corresponding incoming bit stream from a corresponding data I/O block. The FIFO controller controls operations of the one or more FIFOs, such that (i) bits from the corresponding data I/O block are written into the at least one FIFO using a FIFO write clock that is based on an incoming clock signal and (ii) bits are read out from the at least one FIFO using a FIFO read clock that is based on a local reference clock signal.

REFERENCES:
patent: 5835443 (1998-11-01), Fujita
patent: 7184360 (2007-02-01), Gregorius et al.

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