Distributed front-end FIFO for source-synchronized...

Details Distributed front-end FIFO for source-synchronized... Distributed front-end FIFO for source-synchronized...

2007-07-16

2009-08-11

Dinh, Son (Department: 2824)

Static information storage and retrieval

Read/write circuit

Serial read/write

C365S189050, C365S189020, C365S189070, C365S233100

Reexamination Certificate

active

07573770

ABSTRACT:
In one embodiment of the invention, an integrated circuit, such as an FPGA, comprises a distributed FIFO architecture that supports data transfer from an external device, such as an SDRAM, via an interface that receives a non-continuous, asynchronous strobe clock and a data lane having a plurality of bit lines from the external device. The distributed FIFO architecture comprise a FIFO for each bit line and a FIFO controller. Under control of the FIFO controller, data is written into each FIFO using a FIFO write clock based on the strobe clock, while data is read out from each FIFO using a FIFO read clock based on a local reference clock of the integrated circuit. The distributed FIFO architecture is designed to handle a range of possible phase differences between the FIFO write and read clocks to safely convert from the asynchronous, non-continuous strobe domain to a local continuous clock domain.

REFERENCES:
patent: 7009433 (2006-03-01), Zhang
patent: 7109756 (2006-09-01), Zhang
patent: 7221613 (2007-05-01), Pelley et al.
patent: 2006/0050827 (2006-03-01), Saeki et al.

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