Distributed FIFO

Details Distributed FIFO Distributed FIFO

2008-06-30

2010-12-28

Elmore, Stephen C (Department: 2185)

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

C711S005000, C711S100000, C711S149000, C711S151000, C711S158000, C711S173000, C711S137000, C365S221000, C365S230030, C326S040000

Reexamination Certificate

active

07861039

ABSTRACT:
Circuits, methods, and apparatus for FIFO memories made up of multiple local memory arrays. These embodiments limit the number and length of interconnect lines that are necessary to join two or more local memory arrays into a single, larger functional unit. One exemplary embodiment of the present invention provides a FIFO made up of a number of FIFO sub-blocks connected in series. Each FIFO sub-block includes local read and write address counters such that read and write addresses are not bused between the FIFO sub-blocks.

REFERENCES:
patent: 4933901 (1990-06-01), Tai et al.
patent: 4942553 (1990-07-01), Dalrymple et al.
patent: 5235595 (1993-08-01), O'Dowd
patent: 5506747 (1996-04-01), Bain
patent: 5706482 (1998-01-01), Matsushima et al.
patent: 6119207 (2000-09-01), Chee
patent: 6819651 (2004-11-01), Hojo et al.
patent: 6941434 (2005-09-01), Uneyama et al.
patent: 7038952 (2006-05-01), Zack et al.
patent: 7106098 (2006-09-01), Zack et al.
patent: 7161849 (2007-01-01), Lowe et al.
patent: 7254677 (2007-08-01), Lowe et al.
patent: 7406564 (2008-07-01), Bain

Affiliated with

Also associated with

Rating

Distributed FIFO does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Distributed FIFO, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Distributed FIFO will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-4182876