Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
Reexamination Certificate
2008-07-29
2008-07-29
Elmore, Stephen C (Department: 2185)
Electrical computers and digital processing systems: memory
Storage accessing and control
Hierarchical memories
C711S005000, C711S100000, C711S149000, C711S151000, C711S158000, C711S173000, C365S211000, C365S230030, C326S040000
Reexamination Certificate
active
11211038
ABSTRACT:
Circuits, methods, and apparatus for FIFO memories made up of multiple local memory arrays. These embodiments limit the number and length of interconnect lines that are necessary to join two or more local memory arrays into a single, larger functional unit. One exemplary embodiment of the present invention provides a FIFO made up of a number of FIFO sub-blocks connected in series. Each FIFO sub-block includes local read and write address counters such that read and write addresses are not bused between the FIFO sub-blocks.
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Altera Corporation
Elmore Stephen C
Townsend and Townsend / and Crew LLP
Zigmant J. Matthew
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