Electrical computers and digital processing systems: memory – Storage accessing and control – Shared memory area
Reexamination Certificate
2002-02-22
2004-06-22
Gossage, Glenn (Department: 2187)
Electrical computers and digital processing systems: memory
Storage accessing and control
Shared memory area
C711S147000, C709S215000
Reexamination Certificate
active
06754789
ABSTRACT:
BACKGROUND
Shared memory applications often involve a single physical memory used by multiple devices such as, for example, microprocessors. Specialized hardware is typically needed to resolve issues such as, for example, access conflicts when two or more devices attempt to store data simultaneously. Such an approach may be expensive when sharing data among physically dispersed monitoring and control nodes connected over a low speed communications network.
SUMMARY
The following description relates to shared memory, and in particular to information sharing among nodes of a communications network.
Memory space may be shared in a robust manner among multiple devices connected to a communications network by maintaining shared information in a number of individual network nodes. Each participating device is connected to the communications network and has a memory configured to store data provided by participating devices. Arbitrary amounts of memory may be shared. Also, the data shared may include any type of data such as, for example, floating point numbers, signed and unsigned integers of any length, characters, bytes, bits, collections of bits, and data structures.
Techniques are used to provide for data arbitration issues. For example, the memory may have a number of segments pre-allocated to store information provided by participating devices connected to the communications network. Each device is responsible for updating its allocated memory block on other devices. Only one device may be permitted to update a given memory segment, but the memory segment is visible to other participating devices and may be read and used by the other devices.
A broadcast mechanism such as, for example, a Modbus-based broadcast command, may be used to publish the contents of a device's allocated memory block to other devices. Techniques are used for resolving network collisions, arbitrating network access rights, and recovering from faults such as, for example, a communications link failure or a device failure. For example, a round robin scheme may be employed using a memory-address-based bus ownership mechanism and a timeout mechanism. Also, where the physical layer of the communications network is capable of detecting and arbitrating network access collisions, each device may attempt to transmit its data segment as soon as it becomes available.
Techniques are used for detecting and reporting communications errors. For example, an indication of data validity may be provided and associated with the data provided by a participating device, which allows for detecting and reporting errors. Also, the detection and reporting of errors at a device permits that device to make decisions based upon the best available set of valid data.
Such a system may be used in many contexts such as, for example, in the control, supervision and protection of a power system network or in the control and supervision of an industrial process.
In one general aspect, memory sharing includes providing a first device and one or more additional devices. Each device has a memory and is configured to be connected to a network. A portion of the first device memory is allocated, and may be divided into two or more first device memory segments. Each first device memory segment corresponds to a device, and at least one of the first device memory segments corresponds to an additional device. A portion of the additional device memory is allocated, and may be divided into two or more additional device memory segments. Each additional device memory segment corresponds to a device, and at least one additional device memory segment corresponds to the first device. A first device data segment is provided to the additional device, and a first device data validity indication is derived at the additional device. The first device data validity indication is associated with the first device data segment, and the additional device memory segment corresponding to the first device is updated based on the association.
Implementations may include one or more of the following features. For example, a decision may be made by the additional device based at least in part upon the updated additional device memory segment corresponding to the first device. The decision may be used, for example, at least in part to supervise, control, or protect a power system, or to supervise and control an industrial process.
In another implementation, the first device data segment may be provided periodically to the additional devices. The size of the memory portion allocated for each device may be equal to or different from the size of the memory allocated for every other device. Also, the size of the memory segment for one device may be equal to or different from the size of the memory segment of another device.
In another implementation, the network may include a serial data link with the devices physically dispersed from one another. The first device data segment may be provided using the Modbus protocol, and the first device may provide an error checking mechanism to the additional device. Also, the first device validity indication may be derived by the additional device based upon reception of the first device data segment by the additional device.
In yet another implementation, an additional device data segment may be provided to the first device, and an additional device data validity indication may be derived by the first device. The additional device data validity indication is associated with the additional device data segment, and the first device memory segment corresponding to the additional device is updated based upon the association. The additional device data segment may be provided periodically to the first device.
In another general aspect, memory sharing includes providing two or more participating devices. Each participating device has a memory and is configured to be connected to a network. A portion of the memory of each participating device is allocated, and the allocated portion of memory has two or more memory segments, each of which corresponds to a participating device. A data segment is provided from one participating device to all other participating devices. A data validity indication is derived for the data segment at each participating device. The data validity indication is associated with the data segment, and the memory segment corresponding to the provided data segment is updated.
In one implementation, each participating device is assigned a transmission sequence indicator, and data segments from the participating devices are sequentially provided by providing a data segment from one participating device to all other participating devices according to the transmission sequence indicator. The transmission sequence indicator may be based on the address of the memory segment corresponding to the participating device.
In another implementation, a designated timeslot is provided for each participating device to provide a data segment corresponding to that device. A transmission timeout counter is provided and initiated. The timeslot is monitored for provision of a data segment by the appropriate participating device, and the next device in sequence provides a data segment based upon the expiration of the transmission timeout counter and the failure of the appropriate participating device to provide a data segment.
Other features and advantages will be apparent from the description and drawings, and from the claims.
REFERENCES:
patent: 4495493 (1985-01-01), Segarra et al.
patent: 4926375 (1990-05-01), Mercer et al.
patent: 5202970 (1993-04-01), Schiffleger
patent: 5761413 (1998-06-01), Frank et al.
patent: 5761729 (1998-06-01), Scales
patent: 5793750 (1998-08-01), Schweitzer, III et al.
patent: 5893161 (1999-04-01), McGuffey et al.
patent: 6085295 (2000-07-01), Ekanadham et al.
patent: 6360303 (2002-03-01), Wisler et al.
patent: 2002/0029800 (2002-03-01), West
H.E. Bal, Programming Languages for Distributed Computing Systems, ACM Computing Surveys, vol. 21, No.3, Sep. 1989.
Day Timothy Robert
Lee Eric Arden
Skendzic Veselin
Fish & Richardson P.C.
Gossage Glenn
McGraw-Edison Company
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