Electrical computers and digital processing systems: memory – Storage accessing and control – Specific memory composition
Patent
1995-12-27
1998-07-28
Swann, Tod R.
Electrical computers and digital processing systems: memory
Storage accessing and control
Specific memory composition
711148, 711113, 711114, 371 4015, 39520031, 39520081, 39520083, 395293, 395308, 395730, 39580028, G06F 13368
Patent
active
057874590
ABSTRACT:
A RAID-compatible data storage system which allows incremental increases in storage capacity at a cost that is proportional to the increase in capacity. The system does not require changes to the host system. The control and interface functions previously performed by a single (or redundant) central data storage device controller are distributed among a number of modular control units (MCUs). Each MCU is preferably physically coupled to a data storage device to form a basic, low-cost integrated storage node. One of two bus ports interfaces an MCU with the host computer on a host bus, and the other bus port interfaces an MCU with one or more data storage devices coupled to the MCU by a data storage device bus. The serial interface ports provide a means by which each of the MCUs may communicate with each other MCU to facilitate the implementation of a memory array architecture. The entire data storage array may appear as a single device capable of responding to a single identification number on the host bus, or may appear as a number of independent device. A controlling MCU receives a command and notifies the other MCUs that are involved in a read or write operation. Control of the host bus is transferred from one MCU to the next MCU in sequence so that the data is received by the host computer, or written to each data storage device, in the proper order.
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Brant William A.
Hall Randy
Stallmo David C.
Bachand, Esq. Richard A.
EMC Corporation
Kubida, Esq. William J.
Swann Tod R.
Tran Denise
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