Static information storage and retrieval – Systems using particular element – Flip-flop
Reexamination Certificate
2000-01-27
2001-06-05
Nelms, David (Department: 2818)
Static information storage and retrieval
Systems using particular element
Flip-flop
C365S051000, C365S189020, C365S230030
Reexamination Certificate
active
06243287
ABSTRACT:
FIELD OF THE INVENTION
The present invention generally relates to memory management and storage in a computer or other system that uses static random access memory (SRAM), and more particularly, to a distributed decode system and method for improving SRAM density.
BACKGROUND OF THE INVENTION
A typical random access memory (RAM; e.g., static RAM (SRAM) or dynamic RAM (DRAM)) system for a computer includes an array with one or more columns of SRAM cells configured to store respective logic states, i.e., either a logic high (logical “1”) or a logic low (logical “0”). Data is written to and/or read from each of the SRAM cells in each column via differential complimentary bit and nbit connections. An address wordline, which is decoded from a computer address sent by a central processing unit (CPU) or other processor, is communicated to the SRAM cells. The address wordline particularly identifies and enables a specific SRAM cell during each reading and writing operation.
A write driver is designed to write data to a specific SRAM cell that is identified by an address wordline. The bit and nbit connections are initially precharged. In order to write a logic state to a particular SRAM cell, the write driver discharges one of the bit and nbit connections while maintaining the state of the other, in order to create a voltage differential between the connections and instill a particular logic state in the SRAM cell.
A sense amplifier is utilized to retrieve data from SRAM cells. The sense amplifier is typically a differential amplifier. It receives the differential complimentary signals on the bit and nbit connections and can read the stored logic state based upon the voltage differential and polarity between the connections. The sense amplifier produces a data output when prompted to do so by a strobe control signal. The strobe control signal can be a clock edge generated by some type of a timing control unit.
In order to create high-density memories requiring little space, storage elements are often made with the fewest and smallest parts possible. A problem exists, however, in that a high number of decoders are required to access the desired address wordline and column to enable a specific SRAM cell in the array. The use of the large number of decoders imposes a substantial size and component count burden on the chip. Moreover, because the arrays of memory cells in these types of configurations are large, the decoders that are required to drive signals across the arrays to overcome the resistance of the signal wires must also be large. This configuration requires large decoders to maintain the “sweet spot” which is commonly known as the optimal relationship between the resistance of the signal wires to the size of the driver that is required to overcome the resistance. Consequently, the large number of decoders required to properly address the multitude of SRAM cells combined with the requirement that the decoders themselves must be large to maintain the sweet spot, the number of SRAM cells that can be placed on a single chip is substantially limited.
In order to improve the density of SRAM cells relative to speed, a heretofore unaddressed need exists in the industry for an improved SRAM system that increases speed and reduces size and the number of required components in the chip.
SUMMARY OF THE INVENTION
An object of the invention is to overcome the deficiencies and inadequacies of the prior art, as described previously in the background section. Briefly described, the present invention provides for distributed decode system and method for improving static random access memory (SRAM) density.
With respect to architecture, the system is implemented as follows. The system includes a plurality of groups of memory cells. The groups of memory cells are comprised of first and second pluralities of memory cell columns whereby each of the columns include at least one memory cell. The individual memory cells are configured to read and write a respective logic state. The system further includes a sense amplifier in each of the groups, and it is coupled between the first and second pluralities of memory cell columns. A column multiplexer is included in each of the groups of memory cells and is coupled to the first and second pluralities of memory cell columns and the sense amplifier. Additionally, the system includes a global decoder centrally coupled to the groups of memory cells, and it is configured to select any individual said memory cell in any of the groups of memory cells according to an address instruction executed by said global decoder.
The global decoder comprises a first logic block to enable one of the columns of memory cells in one of the groups of memory cells. A second logic block is included in the global decoder to enable one of a plurality of wordlines contained in each of the groups of memory cells to either read or write a specific logic state. Thus, the first and second logic blocks in the global decoder enable one memory cell contained in the groups of memory cells by activating a particular column and wordline in the SRAM array. Once the memory cell is addressed, a logic one or a logic zero may either be written to or read from the memory cell.
An alternative embodiment of the invention provides for multiple signal paths originating from the second logic block coupled to each wordline so that each wordline includes two connection points for receiving data information. Including two signal paths from the second logic block to each wordline of each groups of wordlines eliminates any data transmission delay caused by the natural resistance and capacitance in the wordline.
Still another embodiment includes a local buffer contained in each of the groups of memory cells to perform a final stage of decode. The local buffer comprises a first local group logic block that receives input from the first logic block of the global decoder for selecting the desired column of memory cells. The local buffer also includes a second local group logic block that receives input from the second logic block of the global decoder for selecting the individual wordline contained in that particular group of memory cells. The first and second local group logic blocks only select the column and row respectively when enabled by a local group enable line contained in the local buffer. The local group enable line receives input from a third logic block contained in the global decoder which enables one group while disabling the others. If the third logic block sends a high signal to a particular group, then that group is the group that contains the desired memory cells for writing or reading a logic state to the exclusion of all other groups.
Still another embodiment involves including a third local group logic block in the local buffer so that each wordline receives the data at two points as described above. This embodiment effectively eliminates any delay caused by resistance or capacitance in long wordlines.
The invention has numerous advantages, a few of which are delineated hereafter, as merely examples.
An advantage of the invention is that it improves the speed of SRAM designs by requiring a fewer number of blocks through which to route signals.
Another advantage of the invention is that the density of the memory cells on the SRAM chip is greater because the invention minimizes the number of components required for implementation of a SRAM, particularly, significantly reducing the number of decoders required to access each individual SRAM cell.
Another advantage of the invention is that it is simple in design, reliable in operation, and easily implemented in mass production.
Other objects, features, and advantages of the present invention will become apparent to one with skill in the art upon examination of the following drawings and detailed description. It is intended that all such additional objects, features, and advantages be included herein within the scope of the present invention, as defined by the claims.
REFERENCES:
patent: 5765214 (1998-06-01), Sywyk
patent: 5787041 (1998-07-01), H
Naffziger Samuel D
Weiss Donald R
Wuu John
Hewlett--Packard Company
Ho Hoai V.
Nelms David
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