Electrical computers and digital processing systems: memory – Storage accessing and control – Specific memory composition
Patent
1997-01-21
1998-11-10
Swann, Tod R.
Electrical computers and digital processing systems: memory
Storage accessing and control
Specific memory composition
711 3, 711118, 711130, 711139, 711144, 707200, G06F 1200
Patent
active
058359427
ABSTRACT:
A cache is distributed among processors in a multiple processor system with no shared memory to maintain the cached data. Each processor maintains a cache which identifies the opened files being cached, the blocks of each file which are cached and the state of caching for each file. The state of each opened file is one of "no-caching", "read-caching" and "read/write caching". So long as only one processor opens a file, and opens it for read/write access, that processor is allowed to do read/write caching on the file. When a processor opens a file for read access, that processor is allowed to do read caching, unless another processor has the file open for read/write access. After the last processor having read/write access to a file closes the file, the disk system upgrades the cache state for the file. The downgrading of the caching state is communicated via an asynchronous cache callback signal, while the upgrading of a cache is not indicated to a processor until the processor sends a disk request for the file. The reply to the request contains the new cache state.
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Albert Philip H.
Swann Tod R.
Tandem Computers Incorporated
Thai Tuan V.
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