Electrical computers and digital data processing systems: input/ – Input/output data processing – Input/output access regulation
Utility Patent
1998-08-11
2001-01-02
Sheikh, Ayaz R. (Department: 2781)
Electrical computers and digital data processing systems: input/
Input/output data processing
Input/output access regulation
C710S002000, C710S005000, C710S030000, C710S108000, C710S105000, C710S108000, C710S120000, C710S120000, C710S260000, C710S268000, C709S217000, C709S218000, C709S219000, C709S201000
Utility Patent
active
06170025
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates generally to computers, and more particularly to communications between interconnected computer nodes, storage subsystems, and other network devices.
Assessments of server and I/O technologies and their respective marketplaces make clear that cluster communications, including server-to-server communications and server-to-I/O communications, will be increasingly based on a distributed model. Existing server architectures, based on a shared-address-space model, bus-oriented connections to I/O devices and I/O transactions based on a load/store memory model, have limitations.
FIG. 1
illustrates a block diagram of a current generation computer, including CPUs
105
and
110
connected to a host bus
111
. CPU
105
is connected to a cache
106
and CPU
110
is connected to a cache
108
. The system also includes main memory
109
, and one or two host/PCI bridges
112
and
115
. Host/PCI bridges
112
,
115
convert transactions between host bus
111
and a Peripheral Component Interconnect (PCI) bus
113
. A storage controller
324
and several I/O devices
120
,
122
and
124
are connected to PCI bus
113
. I/O devices
326
are also connected to storage controller
324
.
There are limitations on the number of electrical loads which may be placed on the host bus
111
. Moreover, these configurations are also limited by the PCI bus
113
, which imposes limits both on the number of electrical loads it is capable of supporting and the physical distances at which devices can be placed. As illustrated in
FIG. 1
, storage connectivity and proximity are typically restricted to what fits within a single enclosure.
An architecture for I/O pass through of the present invention overcomes some of the disadvantages and limitations of prior art computer systems by increasing the number of I/O devices that can be connected to a computer system, by increasing the distance at which the I/O devices are located, and by permitting a more distributed architecture. The distributed computer system of the present invention increases the number of I/O devices and the distance at which they are coupled to host computers, while retaining some of the features of current I/O buses, such as PCI.
SUMMARY OF THE INVENTION
According to an embodiment of the present invention, a method of executing a locked transaction over a distributed computer system to a remotely located I/O resource is provided. The distributed computer system includes a host computer and a remotely located I/O resource. The method includes the steps of detecting a locked host transaction on a host computer that is targeted to a remotely located I/O resource, wrapping the locked transaction in a packet for transmission over a network. The packet includes a field indicating that the transaction is locked. The method also includes the steps of transmitting the packet over the network to the remote I/O device, unwrapping the packet received at the I/O device, converting the locked host transaction to a locked I/O transaction and determining if the targeted resource is already locked by another host. In addition, if the targeted I/O resource is not locked by another host computer, then the locked transaction is replayed to the targeted I/O resource.
According to another embodiment of the present invention, a method of processing a remote interrupt in a distributed computer system is provided. The distributed computer system includes a host computer and a plurality of remotely located I/O devices. The method includes the steps of generating an interrupt at one of the remote I/O devices, wrapping and transporting the interrupt to the host computer, unwrapping and replaying the interrupt to the host computer and generating, wrapping and transmitting one or more host read transactions to one or more remote I/O devices in response to the replayed interrupt. In addition, the method includes he steps of unwrapping and replaying the read transactions to the one or more remote I/O devices, obtaining information identifying the I/O device that generated the interrupt and wrapping and transmitting the information identifying the I/O device that generated the interrupt to the host computer. The method also includes the step of executing an interrupt service routine associated with the I/O device that generated the interrupt based on the information identifying the I/O device.
REFERENCES:
patent: 5193189 (1993-03-01), Flood et al.
patent: 5859980 (1999-01-01), Kalkunte
patent: 5915104 (1999-06-01), Miller
patent: 5933413 (1999-08-01), Merchant et al.
patent: 5953511 (1999-09-01), Sescila, III et al.
Drottar Ken
Dunning David S.
Futral William T.
Brake R. Edward
Dharia Rupal D.
Intel Corporation
Sheikh Ayaz R.
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