Distributed clock network using all-digital master-slave...

Details Distributed clock network using all-digital master-slave... Distributed clock network using all-digital master-slave...

2006-11-21

2006-11-21

Ghayour, Mohammed (Department: 2611)

Pulse or digital communications

Synchronizers

Phase displacement, slip or jitter correction

C327S149000, C713S401000

Reexamination Certificate

active

07139348

ABSTRACT:
A distributed clock circuit for clocking high speed data at various different physical locations on a chip while improving setup and hold times. The clock circuit includes a master delay lock loop (DLL) circuit configured to lock a global clock signal with a first data signal, and output a clock delay control signal when the global clock signal is locked. The clock circuit further includes one or more slave DLL circuits, coupled to receive the clock delay control signal to lock a local clock signal with a local data signal, wherein the local clock signal is based on the global clock signal.

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