Static information storage and retrieval – Read/write circuit – Including reference or bias voltage generator
Reexamination Certificate
2000-08-31
2002-12-17
Elms, Richard (Department: 2824)
Static information storage and retrieval
Read/write circuit
Including reference or bias voltage generator
C365S149000
Reexamination Certificate
active
06496421
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to the field of semiconductor memory devices and, more particularly to semiconductor memory devices having a distributed cell plate and/or digit line equilibrate voltage generator.
2. Description of the Related Art
FIG. 1
illustrates a portion of a dynamic random access memory (DRAM) device
300
. The DRAM
300
includes a plurality of dynamic memory cells
312
, a plurality of word lines
314
and a plurality of bit lines
316
. For convenience purposes, only two memory cells
312
, word lines
314
and bit lines
316
are illustrated in FIG.
1
.
The memory cells
312
are organized as an array of columns and rows. Each column typically includes numerous memory cell pairs, such as the single pair illustrated in FIG.
1
. Although not illustrated, a typical column may contain
1024
or
2048
pairs of memory cells
312
. Each memory cell
312
comprises a storage cell
320
(e.g., a capacitor) and an access device
322
, which is typically a metal oxide semiconductor field effect transistor (MOSFET).
Two supply voltages are usually required to operate and access a DRAM cell
312
. The first supply voltage is typically a ground and the second supply voltage is typically referred to as Vcc. A first side or cell plate of the storage cell
320
is connected to an intermediate cell plate reference voltage DVC
2
having a potential between Vcc and ground. This cell plate reference voltage DVC
2
is typically equal to Vcc/
2
, or the average of the first and second memory cell supply voltages. The cell plate reference voltage DVC
2
is produced by a cell plate generator circuit (not shown). The first cell plates of all of the storage cells
320
are typically connected to the cell plate reference voltage DVC
2
.
A second side of each storage cell
320
is connected to one active terminal of an access device
322
. One of the bit lines
316
is connected to the other active terminal of the access device
322
. The gate or control terminal of the access device
322
is connected to one of the word lines
314
. Thus, each memory cell
312
is connected to a word line
314
and a bit line
316
. The word lines
314
and bit lines
316
form a two-dimensional array having a plurality of intersections. A single memory cell
312
corresponds to each intersection. At an intersection, a word line
314
is used to selectively activate the corresponding memory cell
312
. Activating the memory cell
312
connects its storage cell
320
to the corresponding bit line
316
, which allows conventional memory access operations (e.g., data read, data write and refresh) to occur.
The illustrated DRAM
300
also contains an equilibrate circuit
330
. The equilibrate circuit
330
includes two MOSFET transistors
332
,
334
. One active terminal of each of each transistor
332
,
334
is connected to receive the cell plate reference voltage DVC
2
. The other active terminal of each transistor
332
,
334
is connected to one of the adjacent bit lines
316
. The equilibrate circuit
330
is responsive to an equilibrate signal EQ to simultaneously connect the reference voltage DVC
2
to the bit lines
316
. During normal memory access operations, the equilibrate signal EQ is activated to “precharge” the bit lines
316
to the reference voltage DVC
2
prior to activating the corresponding access transistor
322
and accessing the memory cells
312
.
Typically, the first cell plate of each storage cell
320
is maintained at the non-varying cell plate reference voltage DVC
2
. The second cell plate is charged to either the first memory cell supply voltage or the second memory cell supply voltage, depending on whether a “0” or “1” is being written to the cell
320
. Data is read from the cells
312
of the DRAM
300
by activating a word line
314
(via a row decoder), which couples all of the memory cells
312
corresponding to that word line
314
to respective bit lines
316
, which define the columns of the array. One or more bit lines
316
are also activated. When a particular word line
314
is activated, sense amplifier circuitry connected to a bit line
316
detects and amplifies the data bit transferred from the storage cell
320
to its bit line
316
by measuring the potential difference between the activated bit line
316
and a reference line which may be an inactive bit line. The operation of typical DRAM sense amplifier circuitry is described, for example, in U.S. Pat. Nos.5,627,785; 5,280,205; and 5,042,011, all assigned to Micron Technology Inc., and incorporated by reference herein.
While the DRAM
300
has proven to be a reliable architecture, it is not without its shortcomings. For example, the reference voltage DVC
2
is generated by a centralized voltage generator circuit within the array of the DRAM
300
. If the array is divided into subarrays, then the DRAM may contain multiple voltage generator circuits. Reference voltage DVC
2
lines are then fanned out to the components of the array/subarrays. The voltage generator circuit is relatively large and consumes precious space within the array. There is a desire and need to reduce the amount of space used by the voltage generator circuitry in the array of the DRAM
300
.
In addition, the reference voltage DVC
2
generated by the voltage generator circuit may swell or experience dips in different portions of the DRAM
300
. That is, different sections of the memory array will have different voltage levels. This adversely effects the operation of the standard DRAM functions such as reads, writes and precharging. Accordingly, there is a desire and need to reduce the amount of reference voltage swells and dips experienced in today's DRAM arrays.
Another problem experienced by the conventional DRAM
300
is bit line coupling. With the current DRAM configuration, the cell plates of the storage cells
320
move, which couples noise onto the bit lines
316
. If there is too much movement, there will be too much noise on the bit lines
316
. Bit line coupling creates memory cell margin problems, and are a direct result of the current centralized voltage generator techniques. Accordingly, there is a desire and need for a DRAM having a voltage generator circuit that reduces bit line coupling within its arrays.
SUMMARY OF THE INVENTION
The present invention provides voltage generator circuitry that substantially reduces the amount of reference voltage swells and dips in a DRAM memory array.
The present invention further provides voltage generator circuitry that substantially reduces bit line coupling within a DRAM memory array.
The above and other features and advantages of the invention are achieved by providing a voltage reference circuit in the periphery of a memory array. Each subarray of the memory array is associated with a respective voltage driver circuit responsible for generating the cell plate and equilibrate reference voltage for the memory cells in the subarray. The voltage reference circuit is connected to and controls each voltage driver so that each driver generates the proper reference voltage. The distributed circuitry substantially reduces the amount of space used within the memory array while mitigating the problems of prior art voltage generator circuits.
REFERENCES:
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patent: 5274276 (1993-12-01), Casper et al.
patent: 5280205 (1994-01-01), Green et al.
patent: 5500824 (1996-03-01), Fink
patent: 5627785 (1997-05-01), Gilliam et al.
patent: 5640340 (1997-06-01), Fink
patent: 5771188 (1998-06-01), Fink
patent: 5787044 (1998-07-01), Duesman
patent: 5841691 (1998-11-01), Fink
patent: 5946257 (1999-08-01), Keeth
Porter Steve
Van De Graaff Scott
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