Distributed address decoding for bus structures

Details Distributed address decoding for bus structures Distributed address decoding for bus structures

1992-11-12

1994-03-29

Olms, Douglas W.

Multiplex communications

Wide area network

Packet switching

370 67, H04J 302

Patent

active

052991962

ABSTRACT:
A method and an apparatus decodes the address of a selected destination user in a time-distributed manner thereby allowing a faster bus cycle and providing earlier error detection. The method and system of the present invention provides for the distribution of the address decoding over two bus cycles, rather than one, so that a faster bus cycle is allowed. In addition, the present invention provides address decode circuitry within the bus arbitrator/controller so that address decoding and error detection can be performed in parallel with bus arbitration.

REFERENCES:
patent: 4577314 (1986-03-01), Chu et al.
patent: 4939729 (1990-07-01), Weisser
patent: 5083269 (1992-01-01), Syobatake et al.

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