Distributed 4-bits diagonal interleaved parity (DIP4) checker

Details Distributed 4-bits diagonal interleaved parity (DIP4) checker Distributed 4-bits diagonal interleaved parity (DIP4) checker

2006-06-06

2006-06-06

Baker, Stephen M. (Department: 2133)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Error/fault detection technique

Reexamination Certificate

active

07058881

ABSTRACT:
A logic circuit includes an interface and an error detection unit. The interface is configured to receive and transmit a data stream, wherein the data stream includes at least one of a variable length format packet or burst and a fixed length format packet or burst. The error detection unit is configured to detect an error detection code error when a misalignment occurs within the data stream by recursively calculating parity terms.

REFERENCES:
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patent: 5636208 (1997-06-01), Chang et al.
patent: 5751745 (1998-05-01), Chen et al.
patent: 5771249 (1998-06-01), Yanagisawa
patent: 5923653 (1999-07-01), Denton
“Pos-Phy Level 4, A Saturn Packet and Cell Interface Specification for OC192 Sonet/SDH and 10 Gigabit Ethernet”, Interface Specification, PMC-Sierra, Inc., Nr. 6, pp. 1-49, XP002247175, Feb. 2001.

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