Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
1998-12-18
2001-01-30
Carroll, J. (Department: 2811)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S346000
Reexamination Certificate
active
06180978
ABSTRACT:
FIELD OF THE INVENTION
This invention relates to improvements in semiconductor processing techniques, and more particularly to improved semiconductor structures and associated methods for making semiconductor structures, or the like, and still more particularly to improvements in a semiconductor structure, and associated method of making, of CMOS transistors having sub-0.1 micron channel lengths and adequately abrupt junction profiles.
BACKGROUND OF THE INVENTION
Conventional transistor formation processes utilizing ion-implantation to form the channel and source/drain structures do not provide the desired abrupt profiles required to support the formation of CMOS transistors with sub-0.1 micron channel lengths.
One available fabrication method and structure is the conventional ion-implanted channel formation, which acts to control Vt (threshold voltage). The problem with this process and the resulting structure is that the profiles are too deep and not sufficiently abrupt. Controlling the dimensions, and thus the performance characteristics, of the very thin layers is not practical with ion-implantation and subsequent implant anneal steps.
The delta-doped channel also provides insufficient profiles for transistors having sub-0.1 micron channel lengths. In this process, and resulting structure, an undoped epitaxial layer is formed on top of the substrate as the channel region. The problem with this process is that Vt control is essentially governed by the thickness of the undoped layer. For sub-0.1 micron channel lengths, the substrate dopants will diffuse, resulting in undesirably high Vt, unless the layer of epitaxial silicon is thick. If the epitaxial silicon layer is thick, then detrimental short-channel effects will be excessive.
What is needed is a structure, and associated method of making, that provides adequate profiles for transistors having sub-0.1 micron channel lengths.
It is with the foregoing problems in mind that the instant invention was developed.
SUMMARY OF THE INVENTION
The present invention concerns the formation of CMOS transistors, and specifically CMOS transistors having sub-0.1 micron channel lengths, and associated methods for making. The solution to the problems set forth above resides fundamentally in the use of doped epitaxial silicon layers prior to the source/drain formation in a disposable gate CMOS transistor fabrication process. These layers provide desirable Vt control.
The invention discloses structures and methods for disposable-gate CMOS transistors intended for sub-0.1 micron gate length applications. At these short lengths, abrupt source/drain and channel profiles are needed for good transistor performances. For low Vcc, which implies low Vt, and for mid-gap work function gate (TiN), a surface counter-doped channel (“buried layer”) buried channel design is desired. In the present invention, counter-doped epitaxial silicon (doped opposite to the substrate type) is used to form the counter-doped surface layer while maintaining an abrupt channel profile. Shallow source/drain junctions with abrupt source/drain profiles may be formed using raised (or elevated) source/drain design. One problem is connecting the channel to the abrupt source/drain region. In the present invention, three structures and associated methods are disclosed to connect the channel to the abrupt source/drain regions. These three structures starting with a counter-doped epitaxial silicon layer are: 1) drive-in from the source/drain; 2) a groove, defined by a localized oxidation removed by deglaze, in the counter-doped epitaxial layer in the channel; and 3) undercut the pad oxide to expose the source/drain, which subsequently is the overlap region. Techniques (2) and (3) have the additional advantage of resulting in better short-channel transistor characteristics.
In light of the above, therefore, the invention encompasses a transistor structure including a doped silicon substrate, and an oppositely-doped epitaxial silicon layer formed on the substrate. A gate is formed on the epitaxial layer, the gate defining a channel region in the epitaxial layer underneath the gate. A doped layer is formed on the epitaxial silicon layer on opposing sides of, and is isolated from, the gate. The layer, with underlying portions of the epitaxial layer and silicon substrate, forms a source region and a drain region on opposing sides of the gate, with portions of the source region and the drain region in contact with the channel region on opposing sides of the gate. A portion of the gate overlaps a portion of the source region and a portion of the drain region.
In addition, the instant invention encompasses a transistor structure including a doped silicon substrate, an oppositely-doped epitaxial silicon layer formed on the substrate, the epitaxial layer defining a groove therein. A gate is formed over the groove on the epitaxial layer and defines a channel region in the epitaxial layer underneath the gate, with the channel region encompassing the groove. A doped layer is formed on the epitaxial silicon layer on opposing sides of, and is isolated from, the gate. The layer forms a source region and a drain region, each on opposing sides of the gate. Portions of the source region and the drain region are in contact with the channel region on opposing sides of the gate. A first portion of the gate overlaps a portion of the source region and a second portion of the gate overlaps a portion of the drain region.
Further, the instant invention encompasses a transistor structure including a doped silicon substrate, an oppositely-doped epitaxial silicon layer formed on the substrate, and a gate overlying the epitaxial layer and defining a channel region in the epitaxial layer underneath the gate. A doped layer is formed on the epitaxial silicon layer on opposing sides of, and is isolated from, the gate. The layer forms a source region and a drain region, each on opposing sides of the gate. Portions of the source region and the drain region are in contact with the channel region on opposing sides of the gate. A pad oxide layer is formed on the epitaxial layer between the epitaxial layer and the gate layer. The pad oxide layer is also formed on a portion of the source region and the drain region. A first portion of the gate is separated from the source region by the pad oxide layer, and second portion of the gate is separated from the drain region by the pad oxide layer. The first portion of the gate overlaps a portion of the source region, and the second portion of gate overlaps a portion of the drain region.
Further, the instant invention encompasses a gate structure including a doped silicon substrate, an oppositely-doped epitaxial silicon layer formed on the substrate, and a gate formed on the epitaxial layer which defines a channel region in the epitaxial layer underneath the gate. A source region is formed in the epitaxial layer and the doped silicon substrate on one side of the gate. A drain region is formed in the epitaxial layer and the doped silicon substrate on an opposite side of the gate from the source region. A portion of the source region and a portion of the drain region are each in contact with the channel region on opposing sides of the gate. A first portion of the gate overlaps a portion of the source region, and a second portion of the gate overlaps a portion of the drain region.
It is a primary object of the present invention to provide a transistor structure having a counter-doped epitaxial silicon layer as the channel, to allow the formation of abrupt channel profiles.
It is an additional object of the present invention to provide a transistor structure having a counter-doped epitaxial silicon layer as the channel and having an elevated source/drain layer, which allow the formation of abrupt channel profiles.
These and other objects, features, and advantages of the invention will become apparent to those skilled in the art from the following detailed description, when read in conjunction with the accompanying drawings and appended claims.
REFERENCES:
patent: 4419810 (1983-12-01
Chapman Richard A.
Chatterjee Amitava
Murtaza Syed Suhail
Carroll J.
Garner Jacqueline J.
McLarty Peter K.
Telecky, Jr. Fred J.
Texas Instruments Incorporated
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