Computer graphics processing and selective visual display system – Display driving control circuitry – Display power source
Reexamination Certificate
1999-02-18
2004-11-23
Tran, Henry N. (Department: 2674)
Computer graphics processing and selective visual display system
Display driving control circuitry
Display power source
C345S087000, C345S103000, C345S502000, C345S531000
Reexamination Certificate
active
06822647
ABSTRACT:
BACKGROUND OF THE INVENTION
(a) Field of the Invention
The present invention relates to displays having processors for image data, in particular, to liquid crystal displays (LCDs) having processors for storing image data signals from an external device using memory and supplying the image signals to display panels.
(b) Description of the Related Art
Flat panel displays (FPDs) are increasingly used replacing cathode ray tubes (CRTs), and active matrix type LCDs having thin film transistors (TFTs) are widely used among the FPDs.
When image data are stored in a memory and outputted into a display panel, writing and reading of the data are usually synchronized with clock signals having phases synchronized with a horizontal synchronization signal or a vertical synchronization signal. The related techniques are disclosed by Shiki in U.S. Pat. No. 5,406,308. Shiki writes image data in a frame memory in synchronization with a clock signal TCK generated from a horizontal synchronization signal HSYNC supplied from an external image data signal source, and reads the image data from the frame memory in synchronization with the clock signal TCK to supply a liquid crystal display panel.
In the meantime, the speeds or the frequencies of the signals used in systems including the image data signal sources may be different from one another. For example, the frequencies of signals used in the personal computer (PC) systems are different. In particular, display control signals such as horizontal and vertical synchronization signals have various frequencies depending on the system, and the operating speeds of memories differ depending on the system. However, the speeds or the frequencies of driving integrated circuits (ICs) for displays are limited. Accordingly, if both writing and reading of the memory are synchronized with the same clock signal, the output speed from the memory to the driving IC does not depend on the operating speed of the driving IC but depends on the speed of the memory, and this may result in an abnormal operation of the driving IC.
It is an example that the frequency band of the image data signals is higher than the maximum operating frequency of the display. In this case, if both writing and reading of the memory are synchronized with the same clock signal, the reading speed is higher than the operating speed of the driving IC. This causes abnormal operation and short driving time of the driving IC and the images may not be properly displayed.
In the meantime, the reading and writing operation should be performed on time. However, as described above, the discrepancy between various operating speeds of the memories and the limited operating speed of the driving IC in the conventional LCD causes abnormal image display when the vertical refresh speed of the image signal varies.
In addition, when the external image data signals do not enter the conventional display, abnormal images such as fading are displayed on the screen, since the memory is neither read nor written onto. This lowers the reliability of the display.
These disadvantages of the conventional display is predominated in the LCDs where the charging time of the pixels are relatively slow and the driving capacity of the driving IC is limited.
SUMMARY OF THE INVENTION
It is therefore an object of the present invention to prevent abnormal operation of a conventional driving IC.
It is another object of the present invention to provide displays performing stable display regardless of the variation of the vertical synchronization signal of the external image data source.
It is another object of the present invention to provide displays which do not show abnormal image when no image signal is entered.
It is another object of the present invention to easily control displays.
These and other objects, features and advantages are provided, according to the present invention, by writing image data into a memory in synchronization with a control signal synchronized with an external signal source and reading the image data from the memory in synchronization with a control signal independent of the external signal source.
The control signal used in reading the image data is also used for the various signals of the display, i.e., the various signals of the display are divided by the control signal used in reading the image data, and thus the operating speed of the display is always in harmony with the reading speed of the image data, thereby realizing stable images.
Furthermore, the image data read from the memory are in a format suitable for display in writing or reading, to simplify the image processing.
In detail, a display according to the present invention includes a memory storing image data from an external source and a display panel that receives the image data from the memory and displays images. The display also includes a signal generator generating a fist clock signal synchronized with a display control signal from the external source. A write controller generates a write control signal, synchronized with the first clock signal, to control writing of the image data into the memory. An oscillator generates a second clock signal independent of the display control signal, and a read controller generates a read control signal, synchronized with the second clock signal, to control reading of the image data from the memory.
It is preferable that the image data stored in the memory is output in a format determined by the display panel, and it is obtained by using at least one of the write control signal and the read control signal.
It is also preferable that the display panel is driven by the read control signal.
When the display panel is a liquid crystal panel, it is driven in twice-divided mode. In a twice-divided mode, the frequency cycle is reduced to half. For example, when a device operates at a speed of 60 MHz in a normal mode, it operates at a speed of 30 MHz in a twice-divided mode, effectively slowing down the device. Furthermore, the liquid crystal display panel is driven in dual-scanning mode.
The memory preferably has a frame memory.
The display panel may include a device for receiving image data and a device for receiving the read control signal, and the display includes an analog/digital converter converting the image data in an analog format into a digital format when the image data from the external source are in an analog format.
REFERENCES:
patent: 5119083 (1992-06-01), Fujisawa et al.
patent: 5406308 (1995-04-01), Shiki
patent: 5579025 (1996-11-01), Itoh
patent: 5606348 (1997-02-01), Chiu
patent: 5821948 (1998-10-01), Kawamoto et al.
patent: 5861879 (1999-01-01), Shimizu et al.
patent: 5900857 (1999-05-01), Kuwata et al.
patent: 5929832 (1999-07-01), Furukawa et al.
patent: 6040826 (2000-03-01), Furukawa
patent: 6040828 (2000-03-01), Park
patent: 6121947 (2000-09-01), Furuhashi et al.
patent: 6177922 (2001-01-01), Schiefer et al.
patent: 6229516 (2001-05-01), Kim et al.
patent: 8030236 (1996-02-01), None
McGuireWoods LLP
Samsung Electronics Co,. Ltd.
Tran Henry N.
LandOfFree
Displays having processors for image data does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Displays having processors for image data, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Displays having processors for image data will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3291696