Computer graphics processing and selective visual display system – Computer graphics display memory system – Graphic display memory controller
Reexamination Certificate
1998-07-01
2001-08-21
Chauhan, Ulka J. (Department: 2671)
Computer graphics processing and selective visual display system
Computer graphics display memory system
Graphic display memory controller
C345S565000, C345S567000, C345S537000
Reexamination Certificate
active
06278467
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a display memory control apparatuses which is effectively used in information processing apparatuses such as various computers, in particular, in portable appliances in which it is important to lower the amount of power consumption.
2. Description of the Related Art
Information processing apparatuses such as a personal computer, a word processor and the like, have an image display device as a user interface. These information processing apparatuses are provided with a display memory (hereinafter, referred simply to as “VRAM”) for storing data corresponding to an image. In the VRAM, a read for image display is regularly executed, and also, access from a central processing unit (hereinafter, referred simply as to “CPU”) is irregularly executed. For this reason, access control is carried out by means of a display memory control circuit. In a conventional display memory control circuit, a periodical read access to the VRAM is preferentially executed in order to transmit display data to the display device. Therefore, in the case where the CPU makes an access to the VRAM, the CPU is in a wait state until timing other than the periodical read. Under such a control, the processing performance of CPU is not effectively exhibited, and this is one factor of lowering a processing speed.
FIG. 6
schematically shows the prior art which is disclosed in
FIG. 1
of Japanese Unexamined Patent Publication JP-A 7-28990 (1995). As seen from
FIG. 6
, in the prior art, there are provided an address buffer
2
which stores a plurality of addresses at the time of writing from a CPU
1
, and a data buffer
3
which stores a plurality of write data corresponding to these addresses. In order to control these address buffer
2
and data buffer
3
, a buffer control circuit
4
is provided. A bus control circuit
5
executes control between each of the buffers and the CPU
1
. The buffer control circuit
4
executes control for effectively writing the addresses and data stored in each of the address buffer
2
and the data buffer
3
, into a VRAM
6
.
In the prior art, the following proposal has been made. More specifically, a buffer for capturing write data to the VRAM
6
and addresses corresponding to the write data, is provided, and access control is made so as to obtain effective timing of writing the data in the VRAM
6
. By doing so, it is possible to execute access processing without applying a load to the CPU
1
and depending upon the performance of VRAM
6
. In a write sequence to the VRAM
6
, first, when the bus control circuit
5
judges that the data is written from the CPU
1
, the write data and address are stored in the data buffer
3
and the address buffer
2
, respectively. At this time, the address and data mutually make one-to-one correspondence. The address buffer
2
informs the bus control circuit
5
about whether it is empty or full of the content stored as address, by using an internal control signal. And then, the bus control circuit
5
executes control between the CPU
1
and the VRAM
6
on the basis of the signal.
In the prior art, when the data is written in the VRAM
6
from the CPU
1
, VRAM access is carried out the same number of times as CPU access; for this reason, the power of VRAM
6
itself is much consumed. Further, the required number of the address buffers
2
is equal to the number of data buffers
3
; for this reason, this makes large a circuit scale, and also, is one factor of causing an increase in cost and power consumption. Further, in the case where a cache memory is applied as one method for speeding up a memory access, there is required a high speed buffer which can store data corresponding to a plurality of consecutive addresses; for this reason, it is inevitable that a circuit scale will be made larger, and that power consumption and cost will be increased.
SUMMARY OF THE INVENTION
An object of the invention is to provide a display memory control circuit which can control a CPU so that the CPU does not enter a wait state without making large a circuit scale and causing an increase of power consumption.
The present invention provides a display memory control apparatus for controlling access from a CPU and display access to a display memory having a data width plural times a data bus width of the CPU, the display memory control apparatus comprising:
buffer means for storing data in the same number of bits as the data width of the display memory;
buffer control means for controlling data transfer by a plurality of accesses between the CPU and the buffer means;
display control means for periodically reading data from the display memory and displaying the data; and
access control means for making an access to the display memory while regulating read by the display control means from the display memory, and for executing data transfer along the bus width of the display memory between the buffer means and the display memory.
According to the invention, the buffer means is provided between the CPU and the display memory. The display memory has a data width plural times the data bus width of the CPU, and the buffer means can store data in the same number of bits as the display memory data width. Therefore, in the case where the access control means executes data transfer between the display memory and the buffer means, the data equivalent to one address of the display memory is transferred at one time. The transfer of the data equivalent to one address of the display memory between the buffer means and the CPU is executed by a plurality of accesses controlled by the buffer control means. It is not necessary to regulate the plurality of accesses in dependence on read by the display control means from the display memory. In the data transfer requiring an adjustment between the display memory and the buffer means, Data equivalent to data transfer by the plural-time accesses of CPU can be transferred at one time; therefore, it is possible to make small a frequency such that the CPU becomes in a wait state due to the adjustment, and to reduce a power consumed for making an access to the display memory.
According to the invention, by using the VRAM having a multi-bit bus width with respect to the data bus width of the CPU, write data is stored in the VRAM by a fewer number of VRAM accesses. Therefore, it is possible to shorten a waiting time of CPU, and to reduce current consumption of the VRAM itself. Further, as compared with a construction of a general buffer or cache memory, in the write buffer, as many addresses as areas may not be stored therein, so that a circuit scale can be made small.
Further, the invention provides a display memory control apparatus for writing data into a display memory having data lines plural times data lines for making a connection with a CPU, comprising:
a pre-buffer capable of storing addresses and data in writing data into the display memory from the CPU, for deriving a pre-buffer effective flag used as a signal for identifying whether or not addresses and data are stored therein;
a write buffer capable of storing data numerically corresponding to data lines of the display memory while dividing the data between a plurality of areas, for deriving a plurality of effective flags used as a signal for identifying whether or not effective data is stored therein corresponding to respective areas constituting the plurality of areas;
a high-order address buffer for storing a high-order address data of a predetermined number of bits on a high-order side of address;
a low-order address decoder for decoding address of a predetermined number of bits on a low-order side of address;
a high-order address comparator circuit for making a comparison between the high-order address data stored in the high-order address buffer and the high-order address of addresses of the pre-buffer;
an access control circuit for controlling a write operation to the write buffer;
a display control circuit for periodically executing read of display data from the display memory; a
Kuwajima Hidenori
Matsumoto Toshio
Chauhan Ulka J.
Nixon & Vanderhye P.C.
Sharp Kabushiki Kaisha
LandOfFree
Display memory control apparatus does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Display memory control apparatus, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Display memory control apparatus will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2544332