Computer graphics processing and selective visual display system – Plural physical display element control system – Display elements arranged in matrix
Reexamination Certificate
2001-06-12
2004-06-01
Saras, Steven (Department: 2675)
Computer graphics processing and selective visual display system
Plural physical display element control system
Display elements arranged in matrix
C345S094000, C345S096000
Reexamination Certificate
active
06744417
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a display device and a method of driving the same, and more particularly the present invention relates to an active matrix display device that is driven by a dot-line inversion driving method in combination with a dot sequential precharge driving method and a method of driving the same.
2. Description of the Related Art
One known driving method of a display device having pixels arranged in a matrix, such as an active matrix liquid crystal display (LCD), is a dot sequential driving method in which pixels are sequentially driven for one line (one row) on a pixel-by-pixel basis. The dot sequential driving method includes a 1H inversion driving method and a dot inversion driving method.
The 1H inversion driving method experiences the following problems. When video signals are written, resistance exists between horizontally adjacent pixels on lines (hereinafter referred to as “Cs lines”) which distribute a predetermined dc voltage to pixels as a common voltage Vcom, and parasitic capacitance exists at intersections of the Cs lines and signal lines. This causes the video signals to jump over onto the Cs lines or gate lines, resulting in oscillations in the potentials of the Cs lines toward the same polarity as those of the video signals. Therefore, significant horizontal crosstalk or defective shading occurs, leading to significant degradation of the picture quality.
When the pixels maintain pixel information in a period of one field, the potentials of the signal lines oscillate every one horizontal scanning period (1H). In the 1H inversion driving method, the polarities of the video signals written to horizontally adjacent pixels are the same, and the potentials of the signal lines increasingly oscillate. This potential oscillation jumps over to the pixels due to the source-drain coupling of pixel transistors, causing significant vertical crosstalk, and resulting in degradation of the picture quality.
On the other hand, in the dot inversion driving method, video signals having opposite polarities are concurrently written to horizontally adjacent pixels and the potential oscillations of the Cs lines or the signal lines are cancelled out between the adjacent pixels, thereby solving the degradation problem of the picture quality exhibited by the 1H inversion driving method. However, since the polarities of the video signals written to horizontally adjacent pixels are opposite, the fields of the adjacent pixels produce domains (optically dropped regions) at the edges of apertures in the pixels. As a result, the aperture ratio of the pixels is reduced, thus providing a lower transmittance and leading to a reduction in contrast.
In order to address such a deficiency, there has been proposed a driving method termed the “dot-line inversion driving method” in which video signals having polarities opposite to each other are concurrently written to two odd-numbered rows of pixels that are spaced apart, e.g., two rows apart vertically, in adjacent pixel columns so that the polarities of horizontally adjacent pixels are the same while the polarities of vertically adjacent pixels are opposite in the array of pixels to which the video signals have been written.
In the dot-line inversion driving method, video signals having opposite polarities are applied to adjacent signal lines, as in the dot inversion driving method, and the polarities .of horizontally adjacent pixels are the same in the array of pixels to which the video signals have been written, as in the 1H inversion driving method. Therefore, degradation of the picture quality due to horizontal crosstalk or shading can be prevented without having to reduce the aperture ratio of the pixels.
However, when video signals written to pixels are inverted every 1H during the dot sequential driving, a significant charging/discharging current when the video signals are written to the signal line extending along each column of pixels appears as vertical fringes on the display screen. In order to reduce the charging/discharging current during the writing of the video signals as much as possible, a precharge driving method has been adopted in which precharge signals are written in advance before the video signals are written.
In general, gray levels are most likely to produce visible vertical fringes. Therefore, the precharge signal level is typically set at a gray level which is most likely to produce visible vertical fringes. If the precharge signal level is set at a gray level, however, vertical crosstalk occurs when a window pattern and the like are displayed, because the amount of source-drain optical leakage of pixel transistors differs according to location from picture to picture, and results in degradation of the picture quality.
In order to prevent such vertical crosstalk, the precharge signal level should be set at the black level, thereby making the source-drain leakage current of the pixel transistors uniform over the entire screen. If the precharge signal level is set at the black level, however, vertical fringes, as previously described, again appear. In summary, vertical crosstalk and vertical fringes are in a trade-off relation.
Accordingly, a 2-step dot sequential precharge method has been proposed in which a black-level signal and a gray-level signal are precharged in two steps.
FIG. 8
illustrates a circuit structure of a precharge driving circuit
100
in the active matrix liquid crystal display driven by the 2-step dot sequential precharge method.
In
FIG. 8
, the precharge driving circuit
100
includes a shift register
101
and a precharge switching circuit
102
. When a precharge start pulse PST is input, the shift register
101
shifts or transfers the precharge start pulse PST in turn to shift stages (S/Rs) in synchronization with horizontal clocks HCK and HCKX having opposite phases to each other, and successively outputs it as precharge control pulses PCC
1
, PCC
2
, and so on from the shift stages.
The precharge control pulses PCC
1
, PCC
2
, etc. are supplied to the precharge switching circuit
102
. The precharge switching circuit
102
also receives an odd-column precharge black signal PsigBo via a precharge signal line
103
o
, an even-column precharge black signal PsigBe via a precharge signal line
103
e
, an odd-column precharge gray signal PsigGo via a precharge signal line
104
o
, and an even-column precharge gray signal PsigGe via a precharge signal line
104
e.
In the precharge switching circuit
102
, a precharge switch
106
-
1
b
is connected between a signal line
105
-
1
of a pixel section and the precharge signal line
103
o
, a precharge switch
106
-
1
g
is connected between the signal line
105
-
1
and the precharge signal line
104
o
, a precharge switch
106
-
2
b
is connected between a signal line
105
-
2
of the pixel section and the precharge signal line
103
e
, and a precharge switch
106
-
2
g
is connected between the signal line
105
-
2
and the precharge signal line
104
e
. Other precharge switches are further connected in the same way.
The precharge control pulses PCC
1
, PCC
2
, etc. that are output from the shift stages of the shift register
101
are used as drive signals of the precharge switches
106
-
1
b
,
106
-
1
g
,
106
-
2
b
,
106
-
2
g
, etc.
Specifically, the precharge control pulse PCC
1
from the first stage is applied to the precharge switch
106
-
1
b
as a switch driving pulse PSD
1
b
, the precharge control pulse PCC
3
from the third stage is applied to the precharge switch
106
-
1
g
as a switch driving pulse PSD
1
g
, the precharge control pulse PCC
2
from the second stage is applied to the precharge switch
106
-
2
b
as a switch driving pulse PSD
2
b
, and the precharge control pulse PCC
4
from the fourth stage is applied to the precharge switch
106
-
2
g
as a switch driving pulse PSD
2
g
. Other precharge control pulses are further applied in the same way to the subsequent precharge switches.
FIG. 9
is a timing chart of the precharge start pulse PST, the horizon
Kashima Tomohiro
Yamashita Jun-ichi
Alphonse Fritz
Kananen Ronald P.
Rader, Fishman & Grauer P.L.L.C.
Saras Steven
Sony Corporation
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