Computer graphics processing and selective visual display system – Plural physical display element control system – Display elements arranged in matrix
Reexamination Certificate
1999-03-23
2002-03-19
Shalwala, Bipin (Department: 2673)
Computer graphics processing and selective visual display system
Plural physical display element control system
Display elements arranged in matrix
C345S099000, C345S204000
Reexamination Certificate
active
06359607
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to a display device such as a matrix-type liquid crystal display (LCD) device and a display method thereof, and particularly relates to a display device such as an LCD device in which each display pixel is equipped with, for example, a thin film transistor as a switching element, and a display method thereof.
BACKGROUND OF THE INVENTION
LCD devices are widely used as display devices for use in TVs, graphic displays, and the like. Among these, attracting considerable attention are LCD devices in which each display pixel is equipped with a thin film transistor (hereinafter referred to as TFT) as a switching element, since such LCD devices produce display images which undergo no crosstalk between adjacent display pixels even in the case where display pixels therein increase in number.
Such an LCD device includes as main components an LCD panel
1
and a driving circuit section as shown in
FIG. 9
, and the LCD panel is formed by sealing liquid crystal composition between a pair of electrode substrates and applying deflecting plates onto outer surfaces of the electrode substrates.
A TFT array substrate which is one of the electrode substrates is formed by laying a plurality of signal lines S(
1
), S(
2
), . . . S(i), . . . S(N) and a plurality of scanning signal lines G(
1
), G(
2
), . . . G(j), . . . G(M) in a matrix form on a transparent insulating substrate
100
made of glass, for example. At each intersection of the signal lines and the scanning signal lines, a switching element
102
composed of a TFT which is connected with a pixel electrode
103
is formed, and an alignment film is provided so as to cover almost all of them. Thus, the TFT array substrate is formed.
On the other hand, a counter substrate which is the other electrode substrate is formed by laminating a counter electrode
101
and an alignment film all over a transparent insulating substrate made of, for example, glass, as the TFT array substrate. The driving circuit section is composed of a scanning signal line driving circuit
300
, a signal line driving circuit
200
, and a counter electrode driving circuit COM, which are connected with the scanning lines, the signal lines, and the counter electrode of the LCD panel thus formed, respectively. A control circuit
600
is a circuit for controlling both the signal line driving circuit
200
and the scanning signal line driving circuit
300
.
The scanning signal line driving circuit (gate driver)
300
is composed of, for example, a shift register section
3
a
composed of M flip-flops cascaded, and selection switches
3
b
which are opened/closed in accordance with outputs of the flip-flops sent thereto, respectively, as shown in FIG.
10
.
An input terminal VD
1
out of two input terminals of each selection switch
3
b
is supplied with a gate-on voltage Vgh which is enough to cause the switching element
102
(see
FIG. 9
) to attain an ON state, while the other input terminal VD
2
thereof is supplied with a gate-off voltage Vg
1
which is enough to cause the switching element
102
to attain an OFF state. Therefore, gate start signals (GSP) are sequentially transferred through the flip-flops in response to a clock signal (GCK) and are sequentially outputted to the selection switches
3
b
. In response to this, each selection switch
3
b
selects the voltage Vgh for turning on the TFT and outputs it to the scanning signal line
105
during one scanning period (TH), and thereafter outputs the voltage Vg
1
for turning off the TFT to the scanning signal line
105
. With this operation, image signals outputted from the signal line driving circuit
200
to the respective signal lines
104
(see
FIG. 9
) can be written in respective corresponding pixels.
FIG. 11
illustrates an equivalent circuit of a one display pixel P(i, j) in which a pixel capacitor Clc and a supplementary capacitor Cs are connected in parallel to a counter potential VCOM of the counter electrode driving circuit COM. In the figure, Cgd represents a parasitic capacitance between a gate and a drain.
FIG. 12
illustrates driving waveforms of a conventional LCD device. In
FIG. 12
, Vg is a waveform of a signal for one scanning signal line, Vs is a waveform of a signal for one signal line, and Vd is a drain waveform.
Here, the following description will explain a conventional driving method, while referring to
FIGS. 9
,
11
, and
12
. Incidentally, it is widely known that liquid crystal requires alternating current drive so as to avoid occurrence of burn-in residual images and deterioration of displayed images, and the conventional driving method described below is explained by taking as an example a frame inversion drive which is a sort of the alternating current drive.
When a scanning voltage Vgh is applied from the scanning signal line driving circuit
300
to a gate electrode g(i, j) (see
FIG. 9
) of a TFT of one display pixel P(i, j) during a first field (TF
1
) as shown in
FIG. 12
, the TFT attains an ON state, and an image signal voltage Vsp from the signal line driving circuit
200
is applied to a pixel electrode through a source electrode and a drain electrode of the TFT. Until a scanning voltage Vgh is applied during the next field (TF
2
), the pixel electrode maintains a pixel potential Vdp as shown in FIG.
12
. Since the counter electrode has a potential set to a predetermined counter potential VCOM by the counter electrode driving circuit COM, the liquid crystal composition held between the pixel electrode and the counter electrode responds in accordance with a potential difference between the pixel potential Vdp and the counter potential VCOM, whereby image display is carried out.
Likewise, when a scanning voltage Vgh is applied to a TFT gate electrode g(i, j) of one display pixel P(i, j) during the second field (TF
2
) from the scanning signal line driving circuit
300
as shown in
FIG. 12
, the TFT attains an ON state and an image signal voltage Vsn from the signal line driving circuit
200
is written in the pixel electrode. The pixel electrode maintains a pixel potential Vdn, and the liquid crystal composition responds in accordance with a potential difference between the pixel potential Vdn and the counter potential VCOM, whereby image display is carried out while liquid crystal alternating current drive is realized.
Since a parasitic capacitance Cgd is unavoidably formed between the gate and the drain of the TFT out of structural necessity as shown in
FIG. 11
, a level shift Avd caused by the parasitic capacitance Cgd occurs to the pixel potential Vd at a fall of the scanning voltage Vgh, as shown in FIG.
12
. Let a non-scanning voltage (a voltage when the TFT is in the OFF state) of the scanning signal be Vgl, and the level shift &Dgr;vd which thus occurs to the pixel potential Vd, caused by the parasitic capacitance Cgd which is unavoidably formed in the TFT, is expressed as:
&Dgr;Vd=Cgd·
(
Vgh−Vgl
)/(
Clc+Cs+Cgd
)
Since the level shift causes a problem such as flickering of an image and deterioration of display, this is not favorable at all to LCD devices, of which higher definition and higher performance are required.
Therefore, conventionally has been proposed such a measure that the counter potential VCOM of the counter electrode is preliminarily biased so that the level shift &Dgr;Vd caused by the parasitic capacitance Cgd decreases.
By the foregoing conventional technique, however, it is difficult to arrange the scanning signal lines G(
1
), G(
2
), . . . G(j), . . . G(M) in such an ideal form that the scanning signal lines do not undergo signal delay transmission, and hence the scanning signal lines thus arranged results in constituting a signal delay path which undergoes signal delay to some extent.
FIG. 14
is a transmission equivalent circuit diagram in the case where signal transmission delay of one scanning signal line G(j) is focused. In
FIG. 14
, rg
1
, rg
2
, rg
3
, . . . rgN represent resistance components of wire materials forming the scanning signal lines and resistance
Miyata Hidekazu
Morii Hideki
Yanagi Toshihiro
Conlin David G.
Daley, Jr. William J.
Dike, Bronstein, Roberts and Cushman
Osorio Ricardo
Shalwala Bipin
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