Display control circuit

Details Display control circuit Display control circuit

2005-04-06

2008-12-02

Chauhan, Ulka (Department: 2628)

Computer graphics processing and selective visual display system

Computer graphics display memory system

C345S001100, C345S087000, C345S089000, C345S204000, C345S214000, C345S638000, C348S177000, C348S178000, C369S292000, C711S106000

Reexamination Certificate

active

07460127

ABSTRACT:
A display control circuit incorporating a RAM in which display data is stored, comprises an oscillation circuit which oscillates a reference clock to define a transfer period in which the display data is transferred from the RAM to a display and a counter circuit which counts the number of the reference clocks, and the transfer period is determined by the number of counts of the reference clocks by the counter circuit. In addition, the oscillation circuit starts oscillation when a transfer request of the display data is generated while the oscillation is stopped, and stops the oscillation when an access request from the CPU is generated during the oscillation, and resumes the oscillation when the access request is stopped.

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patent: 2002/0033900 (2002-03-01), Honma et al.
patent: 2002/0180675 (2002-12-01), Tobita et al.
patent: 61-208553 (1986-09-01), None
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patent: 8-6546 (1996-01-01), None
patent: 2003288202 (2003-10-01), None

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