Computer graphics processing and selective visual display system – Plural physical display element control system – Display elements arranged in matrix
Reexamination Certificate
1998-12-21
2001-10-30
Chow, Dennis-Doon (Department: 2675)
Computer graphics processing and selective visual display system
Plural physical display element control system
Display elements arranged in matrix
C345S003100, C345S088000
Reexamination Certificate
active
06310597
ABSTRACT:
CLAIM OF PRIORITY
This application makes reference to, incorporates the same herein, and claims all benefits accruing under 35 U.S.C §119 from an application entitled Display Apparatus With Color Video a Control Signal Function earlier filed in the Korean Industrial Property Office on Dec. 19, 1997, and there duly assigned Ser. No. 97-70488 by that Office.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention concerns a display apparatus, and more particularly a display apparatus for converting analog video signals from a host into digital video signals displayed on a liquid crystal display (LCD) panel.
2. Background of the Invention
As the LCD frequently replaces the CRT to display the analog video signals from a computer, there becomes required an apparatus for converting the analog video signals into corresponding digital video signals.
In a conventional LCD video display apparatus, analog RGB video signals, horizontal sync signals and vertical sync signals from a host are input through a connector and amplified by a preamplifier to a TTL level. Then, the amplified analog video signals are converted into corresponding digital video signals and applied to a LCD driver composed of an application-specific integrated circuit (ASIC).
Generally, the maximum level of the video signal input to the LCD display apparatus is about 0.7V, which is amplified by the preamplifier 20 to the TTL level of maximum 5V. However, if video signals of maximum 1.4V are input into such a LCD display apparatus with the input level of 0.7V, the output of the preamplifier becomes 10V at maximum. This causes the generation of saturated digital values (maximum values) for the video signals of more than 0.7V, thereby resulting in distorted images.
U.S. Pat. No. 5,751,261 to Matthew Zavracky et al. and entitled Control System For Display Panels provides an example of a known connector used for supplying the RGB video signals, horizontal sync signals and vertical sync signals from a host computer to a LCD panel.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide a display apparatus for converting the analog color video signals from a computer into corresponding digital video data applied to an LCD panel which includes means for reducing the amplification factor of the preamplifier so as not to saturate the digital video data when the input video signals have the maximum voltage level exceeding a given value.
According to an embodiment of the present invention, a display apparatus for converting the analog video signals from a host into corresponding digital video data applied to an LCD panel, comprises a microprocessor for generating a video level control signal to control the level of the video data, a preamplifier for amplifying the analog video signals according to a given amplification factor control signal, an A/D converter for converting the amplified analog video signals of the preamplifier into corresponding digital video data based on the read clock signal from an input PLL, and an LCD driver for setting the value of the input video data based on the video level control signal to deliver the digital video data from the A/D converter to the LCD panel, wherein the LCD driver generates an amplification factor control signal applied to the preamplifier to reduce the value of the digital video data from the A/D converter when the value of the digital video data is greater than the set value of the input video data. The input PLL generates the read clock signal based on an input phase control signal delivered from the microprocessor. Preferably, an write PLL is further provided to generate an write clock signal based on an output phase control signal delivered from the microprocessor. The amplification factor control signal is preferably pulse-width modulated. The pulse width of the amplification factor control signal is reduced if the value of the digital video data from the A/D converter is greater than the set value of the input video data. The LCD driver is preferably designed to generate the amplification factor control signal for the preamplifier to amplify the analog video signals to 5V at maximum.
According to another embodiment of the present invention, a display apparatus for converting the analog video signals from a host into corresponding digital video data applied to an LCD panel, comprises a microprocessor for generating a video level control signal to control the level of the video data, a preamplifier for amplifying the analog video signals according to a given amplification factor control signal, an AID converter for converting the amplified analog video signals of the preamplifier into corresponding digital video data based on the read clock signal from an input PLL, and an LCD driver for setting the value of the input video data based on the video level control signal to deliver the digital video data from the A/D converter to the LCD panel, wherein the LCD driver generates a first amplification factor control signal when the value of the digital video data is greater than the set value of the input video data, and the microprocessor generates a second amplification factor control signal according to the first amplification factor control signal applied to the preamplifier to reduce the value of the digital video data from the A/D converter. The input PLL generates the read clock signal based on an input phase control signal delivered from the microprocessor. Further included is an write PLL for generating an write clock signal based on an output phase control signal delivered from the microprocessor. The second amplification factor control signal is preferably pulse-width modulated. The LCD driver is preferably designed to generate the first amplification factor control signal applied to the microprocessor for the preamplifier to amplify the analog video signals to 5V at maximum.
The microprocessor generates the input/output phase control signals according to the sync signal from the host together with the reference signal to deal with the level of the color video signal received from the host. The read and write PLLs respectively generate the read and write clock signals according to the input/output phase control signals. The preamplifier is to amplify the level of the color video signal from the host based on the amplification factor control signal. The A/D converter is to convert the amplified analog video signal into corresponding digital video data. The LCD driver generates the amplification factor control signal, according to which the preamplifier is controlled to reduce the amplification factor if the level of the digital video data is over the set value. The LCD driver also transfers the digital video data in response to the write clock signal. Thus, if the maximum level of the analog video signals from the host is over the initially set value, the preamplifier is controlled to reduce the amplification factor so as to prevent the amplified analog video signal from being saturated.
REFERENCES:
patent: 4275421 (1981-06-01), Louie et al.
patent: 5317401 (1994-05-01), Dupont et al.
patent: 5751261 (1998-05-01), Zavracky et al.
patent: 5841430 (1998-11-01), Kurikko
Bushnell , Esq. Robert E.
Chow Dennis-Doon
Samsung Electronics Co,. Ltd.
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