Displacement current trigger SCR

Details Displacement current trigger SCR Displacement current trigger SCR

1999-04-15

2001-07-31

Sherry, Michael J. (Department: 2836)

Electricity: electrical systems and devices

Safety and protection of systems and devices

Transient responsive

C361S056000, C257S360000

Reexamination Certificate

active

06268992

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates to the protection of integrated circuits from electrostatic discharge (ESD), and more particularly to a low voltage protection of CMOS circuits by a parasitic silicon controlled rectifier (SCR) which is triggered by a displacement current.
2. Description of the Related Art
The protection of integrated circuits from electrostatic discharge (ESD) is a subject which has received a lot of attention from circuit designers because of the serious damage that ESD can wreak as oxide thicknesses are reduced together with device dimensions. The seriousness of the problem is reflected in the number of articles published and U.S. Patents issued. Workers in the field and inventors have proposed many solutions, many trying to solve the problem of protecting sub-micron devices while still allowing them to function unencumbered and without undue, or zero, increase of silicon real estate. The main thrust of ESD protection for CMOS devices is focused on the use of parasitic npn and pnp bipolar transistor, which together form an SCR. Unwanted as this SCR is normally, it can safely discharge dangerous ESD voltages as long as its trigger voltage is low enough to protect those CMOS devices of which it is a part. Past solutions have offered low voltage lateral SCRs (LVTSCR), modified lateral SCRs (MLSCR), PMOS-trigger lateral SCRs (PTLSCR), NMOS-trigger lateral SCRs (NTLSCR), and modified PTLSCRs and NTLSCRs.
FIG. 1
is a cross-sectional view of a typical prior art CMOS structure protected from ESD pulses by an SCR and NMOS transistor. Shown is a semiconductor wafer
10
with CMOS devices, with parasitic bipolar transistors forming an SCR, and an additional NMOS device for lowering the trigger voltage of the SCR. In a p-substrate
11
an n-well
12
is formed, and a p-channel transistor with a p
+
source
14
and a p
+
drain (not shown) is created. An n
+
contact region
13
is formed in the n-well and together with p
+
source
14
connected to a voltage supply pad
19
. In p-substrate
11
an n-channel transistor with an n
+
drain
15
, an n
+
source
16
, and a gate
17
is created. The n
+
drain
15
straddles p-substrate
11
and n-well
12
. A p
+
contact region
18
, formed in p-substrate
11
, is connected together with n
+
source
16
to a reference voltage
20
.
The steps that produce the above CMOS structure also create parasitic bipolar pnp transistor
21
between p
+
source
14
(emitter), n-well
12
(base), and p-substrate
11
(collector), and parasitic bipolar npn transistor
22
between n
+
source
16
(emitter), p-substrate
11
(base), and n-well
12
(collector). The base of transistor
21
is connected via n-well resistor
23
to n
+
contact region
13
, and the base of transistor
22
is connected via p-substrate resistor
24
to p
+
contact region
18
. The base of one transistor is connected to the collector of the other transistor. Resistors
23
and
24
are equivalent resistors for the intrinsic resistance of the n-well and p-substrate material.
FIG. 2
is the equivalent circuit of
FIG. 1
showing the interconnection of transistor
21
and
22
forming an SCR. NMOS transistor Q
1
is shunted across npn transistor
22
providing the trigger for the SCR. ESD voltage pulses are shunted from pad
19
via transistors
21
and
22
to reference voltage (ground)
20
.
U.S. Patents relating to ESD protection are:
U.S. Pat. No. 5,754,381 (Ker) provides a modified PTLSCR and NTLSCR, and bypass diodes for protection of the supply voltage and output pad of an output buffer. The trigger voltage is the low snap-back trigger voltage of a short-channel PMOS (NMOS) device.
U.S. Pat. No. 5,754,380 (Ker et al.) is similar to U.S. Pat. No. 5,754,381 above but without bypass diodes. The invention requires a smaller layout area than conventional CMOS output buffers with ESD protection.
U.S. Pat. No. 5,744,842 (Ker) teaches the use of an ESD protection circuit between V
dd
and V
ss
, comprising a bipolar transistor and an n-type field-oxide device.
U.S. Pat. No. 5,742,085 (Yu) discloses a low-voltage trigger protection, consisting of two SCRs and an NMOS transistor for triggering disposed between an IC bonding pad and V
ss
.
U.S. Pat. No. 5,719,733 (Wei et al.) presents an ESD protection device using one SCR for deep submicron CMOS devices, where the structure comprises a p-well and an n-well (or p-substrate) that are separated. A ground electrode is connected to a p
+
and an n
+
contact region and through a polysilicon region to a gate oxide region in the n-well. The triggering voltage for snapback of the SCR is tunable between 5-11 Volts.
U.S. Pat. No. 5,576,557 (Ker et al.) provides ESD protection for sub-micron CMOS devices supplying discharge paths at V
dd
and V
ss
using two LVTSCRs. In addition a PMOS device is used in conjunction with one LVTSCR and an NMOS device with the other LVTSCR. Inclusion of the PMOS and NMOS devices allows lowering of the trigger voltage to 11-13 Volt.
U.S. Pat. No. 5,572,394 (Ker et al.) discloses an ESD protection circuit formed by two PTLSCRs and two NTLSCRs for protection from the four modes of ESD. The use of short-channel thin-oxide PMOS (NMOS) devices reduces the turn-on voltage of the lateral SCR to below the gate-oxide breakdown voltage of CMOS devices in the input stage.
U.S. Pat. No. 5,541,801 (Lee et al.) uses three LVTSCRs which are connected between V
dd
, the circuit to be protected, and V
ss
. Each of the SCRs uses a PMOS/NMOS transistor to lower the trigger voltage. The gates of the PMOS/NMOS transistors are each in turn connected via linked terminals of trigger gates to the circuit to be protected.
U.S. Pat. No. 5,452,171 (Metz et al.) describes a protection circuit using an inverter trigger device, with a voltage divider on its output, to control the amount of voltage necessary to cause latchup of the parasitic SCR. An NMOS device is disposed between the output of the trigger device and the SCR.
U.S. Pat. No. 5,400,202 (Metz et al.) is similar to U.S. Pat. No. 5,452,171 above in the use of an inverter trigger device, an NMOS transistor and the parasitic SCR, but does not appear to use the voltage divider.
It should be noted that none of the above-cited examples of the related art have reduced the snapback voltage below 4 Volt. The snapback voltage of a LVTSCR with a short-channel NMOS (or PMOS) of 4 Volt is still too high to protect the internal circuit of 0.18 micron processes, because the oxide thicknesses are in the order of 32 Ångstrom. The related art does not address protection for oxides that thin. What is needed is an SCR with an trigger voltage in the range of 1.2 Volt. This voltage is low enough to prevent internal device damage by ESD pulses. Instead of the breakdown of an NMOS (or PMOS) device utilizing the breakdown of n-well to p-substrate (or p-well) will be proposed.
SUMMARY OF THE INVENTION
It is an object of the present invention to present circuits and methods which protect CMOS semiconductor devices, having oxides as thin as 32 Ångstrom, from electrostatic discharge (ESD).
Another object of the present invention is to utilize a parasitic silicon controlled rectifier (SCR), intrinsic to the semiconductor device, for the protection.
A further object of the present invention is to provide low voltage triggering of the parasitic SCR in the order of 1.2 Volt.
These objects have been achieved by providing a displacement current trigger which causes components of the SCR (parasitic npn and pnp bipolar transistors) to conduct, i.e., to trigger the SCR. The displacement current is realized by a junction capacitance, which is connected on one side to the pad to be protected and on the other side to terminals of the aforementioned parasitic bipolar transistors. Two ways of realizing the junction capacitance are disclosed.


REFERENCES:
patent: 5400202 (1995-03-01), Metz et al.
patent: 5452171 (1995-09-01), Metz et al.
patent: 5528188 (1996-06-01), Au et al

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