Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital data error correction
Patent
1997-05-15
1999-12-28
Moise, Emmanuel L.
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital data error correction
714775, 360 51, C11C 2900, G11B 509
Patent
active
060095490
ABSTRACT:
A disk storage system is disclosed wherein user data received from a host system is first encoded according to a first channel code having a high code rate, and then encoded according to an ECC code, such as a Reed-Solomon code, wherein the ECC redundancy symbols are encoded according to a second channel code having low error propagation. In the preferred embodiment, the first channel code is a RLL (d,k) code having a long k constraint which allows for longer block lengths (and higher code rates). During read back, a synchronous read channel samples the analog read signal a synchronously and interpolates the asynchronous sample values to generate sample values substantially synchronized to the baud rate. In contrast to conventional synchronous-sampling timing recovery, interpolated timing recovery can tolerate a longer RLL k constraint because it is less sensitive to noise in the read signal and not affected by process variations in fabrication. Additionally, a trellis sequence detector detects an estimated binary sequence from the synchronous sample values, wherein a state transition diagram of the trellis detector is configured according to the code constraints of the first and second channel codes. The estimated binary sequence output by the sequence detector is buffered in a data buffer to facilitate the error detection and correction process, and to allow for retroactive and split-segment symbol synchronization using multiple sync marks.
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Behrens Richard T.
Bliss William G.
Zook Christopher P.
Cirrus Logic Inc.
Moise Emmanuel L.
Sheerin Howard H.
Shifrin Dan A.
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