Electrical computers and digital processing systems: memory – Storage accessing and control – Specific memory composition
Patent
1997-04-28
1999-02-23
Tung, Kee M.
Electrical computers and digital processing systems: memory
Storage accessing and control
Specific memory composition
395847, G06F 1200, G06F 1328
Patent
active
058754580
ABSTRACT:
A disk storage device includes two data buses 100, 200 for data transfer. Hard disks (HDDs) 0 and 1 are permanently connected to the data buses 100, 200, and hard disks 2 and 3 are selectively connectable to either of the data buses. When a microcontroller (MCU) 32 outputs a specified signal to a data path controller (DPC) 10 in response to a command from a host, multiplexers 20, 22 connect the selectively connectable hard disks 2 and 3 to one of the data buses. When data is written to or read from the hard disks, the write or read can be performed quickly with fewer data buses and a simple device configuration. A parity data generator (PGEN) 24 is connected to both of the buses, receiving new data via one bus and writing new parity data via the other bus.
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Munetoh Seiji
Murata Hiroki
Niijima Hideto
Takahashi Nobuaki
Garnett Pryor A.
International Business Machines - Corporation
Tung Kee M.
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