Disk reproducing apparatus

Error detection/correction and fault detection/recovery – Data processing system error or fault handling – Reliability and availability

Reexamination Certificate

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Reexamination Certificate

active

10318157

ABSTRACT:
With regard to two-way clock synchronous serial communication conducted between a back-end microcomputer16and a front-end microcomputer8, data is sent from the front-end microcomputer8to the back-end microcomputer16in a form of responding to data sent from the back-end microcomputer16between the back-end microcomputer16and the front-end microcomputer8and from the sending side, sending target data formed by adding a byte for error detection to a byte which is the original sending target is sent and in the receiving side, when a byte corresponding to the byte for error detection is received, error detection of received data is performed using said byte and when an error is detected in the received data, by providing notification to the effect that a communication error occurrs from the receiving side to the sending side.

REFERENCES:
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patent: 4213201 (1980-07-01), Gagnier et al.
patent: 4398264 (1983-08-01), Couper et al.
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patent: 4920533 (1990-04-01), Dufresne et al.
patent: 5109384 (1992-04-01), Tseung
patent: 5237670 (1993-08-01), Wakerly
patent: 6842433 (2005-01-01), West et al.
patent: 05-073214 (1993-03-01), None
patent: 6-243052 (1994-09-01), None
patent: 07-013880 (1995-01-01), None
patent: 09-233058 (1997-05-01), None
patent: 11-045214 (1999-02-01), None
patent: 2000-201198 (2000-07-01), None
patent: 2000-251260 (2000-09-01), None
patent: 2001-006344 (2001-01-01), None

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