Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
Reexamination Certificate
2002-02-15
2004-08-10
Lane, Jack A. (Department: 2188)
Electrical computers and digital processing systems: memory
Storage accessing and control
Hierarchical memories
C711S129000, C711S137000
Reexamination Certificate
active
06775744
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to device in a subsystem for keeping a rise in costs to a minimum and reducing access time to a memory, thereby improving the performance of the subsystem. In the subsystem, data from a host and parity data are stored in a memory.
Conventionally, as a cache memory contained in a disk memory device, a single type of memory is employed. In the disk memory device, data transferred from the host and parity data generated in the disk memory device are stored. Thus, for both of data processing that has to be performed at a high speed and data processing that may be performed at a low speed, the memory with the same access rate was employed.
There is provided a type of a system equipped with a high-speed storage and a low-speed storage. In this system, the data from the host is first stored in the high-speed storage. Then, if the high-speed storage has become full, the low-speed storage is used next. Among the systems of this type are those disclosed in JP-A-60-146348 and JP-A-3-37747. Generally, high-speed storages are more expensive than the low-speed storages. Under normal conditions, if processing can be performed by the high-speed storage alone, the performance of the system will not degrade. Therefore, the system is configured as follows: instead of using the high-speed memory alone for data processing, the low-speed memory is also employed. Then, for the amount of storage normally used, the high-speed storage is employed, and for the amount of storage more than the storage amount normally used, the low-speed storage is employed. With this arrangement, requirements for performance and cost are both satisfied.
SUMMARY OF THE INVENTION
As the storage capacity of the disk memory device in the form of the subsystem increases due to an increase in the storage capacity of a hard disk, the storage capacity of the cache memory equipped with the disk memory device increases correspondingly. In this situation, if only one type of the memory with an access rate for data processing that has to be performed at a high speed is employed as the cache memory, a considerable rise in costs occurs.
The object of the present invention is to provide a disk memory device equipped with both high-speed memory and low-speed memory, thereby allowing a rise in costs to be kept to a minimum. In this system, for the amount of storage required for data processing that has to be performed at the high speed, the high-speed memory is employed, and for the amount of storage required for data processing that can be safely performed at a low speed, the low-speed memory is employed.
Other objects, features and advantages of the invention will become apparent from the following description of the embodiments of the invention taken in conjunction with the accompanying drawings.
REFERENCES:
patent: 5778430 (1998-07-01), Ish et al.
patent: 6629200 (2003-09-01), Kanamaru et al.
patent: 60-146348 (1985-08-01), None
patent: 3-37747 (1991-02-01), None
patent: 9-305491 (1997-11-01), None
Jiang Xiaoming
Yagi Satoshi
Ho Thang
Lane Jack A.
McDermott Will & Emery LLP
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