Electrical computers and digital processing systems: memory – Storage accessing and control – Specific memory composition
Reexamination Certificate
2001-02-09
2003-09-02
Yoo, Do Hyun (Department: 2187)
Electrical computers and digital processing systems: memory
Storage accessing and control
Specific memory composition
C711S114000, C711S154000, C711S170000
Reexamination Certificate
active
06615313
ABSTRACT:
CROSS REFERENCE TO RELATED APPLICATIONS
The contents of 2000-167483, filed Jun. 5, 2000 in Japan, are incorporated herein by reference.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to an input/output control device for disks, and, more particularly, to an input/output control device that maintains write data in multiple cache memory modules.
2. Description of the Related Art
RAID control devices typically include cache memory. In response to a write request received from a server, the RAID control devices return a write request complete response to the server just by writing the data to the cache memory. The write data stored in the cache memory is written to disk devices asynchronously to the write complete response sent to the server. This type of operation is called a write back operation. The response time of a disk device that uses a cache memory to perform a write back operation in response to a write request is many times (approximately 10 times) shorter than disk devices that have no cache memory.
In order to guarantee permanence of the write data, RAID control devices normally have two cache memory modules and each cache memory module holds its own write data. The write data that is held in the two cache memory modules is referred to as primary data and secondary data below. By using this sort of configuration, even if there is a problem with one of the cache memory modules, the other cache memory module contains write data, so the write data will not be lost.
Normally, in order to guarantee the permanence of the write data, when there is a problem with the cache memory and there is only one cache memory, the write data stored in the cache memory is written back immediately to the disk. In this situation, the writing of the write data to the disk is synchronized and a write data complete response is returned to the server. This sort of operation is referred to as a write through operation. Switching from a write back operation to a write through operation when there is a problem with the cache memory requires a longer period of time (approximately 10 times) to respond to a write request.
One method considered as a countermeasure to the above loss of performance when shifting to a write through operation when having trouble with the cache memory is to prepare a spare cache memory to use when there are cache memory problems.
That is, in addition to two cache memories, Cache
1
102
and Cache
2
107
, shown in FIG.
10
(
a
), a spare cache memory, Cache X
106
, which is not normally used, is prepared.
Then if, for instance, there is a problem with the cache memory Cache
1
102
, the spare cache memory Cache X
106
can be used to hold the primary data and secondary data of the write data, as shown in FIG.
10
(
b
). By using this sort of configuration, even if there are problems with the cache memory Cache
1
102
or Cache
2
107
, the write back operation can be performed. The above system is referred to as a hot spare system
100
.
However, the aforementioned conventional methods have the following disadvantages:
(1) The hot spare system
100
requires that a cache memory module
106
be prepared that is normally not used, as shown in FIG.
11
(
a
), so the cache memory cannot all be used effectively.
(2) To ensure the permanence of the write data, when using two cache memory modules
102
,
107
as described above, the cache memory modules
110
,
112
must always be increased in pairs
108
when expanding the cache memory as shown in FIG.
11
(
b
). In addition, when using the hot spare system
100
, a cache memory module
106
must be prepared that is normally not used.
SUMMARY OF THE INVENTION
An object of the present invention is to solve the above-mentioned problems.
Another object of the present invention is to provide an input/output control device that allows the effective use of all of the cache memory.
A further object of the present invention is to allow the amount of cache memory to be increased one cache memory module at a time.
The present invention comprises a computer system comprising an input/output control device coupled to one or more disk devices and coupled to and receiving a write request including data from a processing device. The input/output control device of the present invention comprises n (n>2) cache memory modules storing the data upon receiving the write request. The input/output control device transmits to the processing device a write request complete response, and, asynchronously with transmitting the write request complete response, stores the data from the cache memory modules to the one or more disk devices. The input/output control device divides the regions of the one or more disk devices into a number of n of the cache memory modules in accordance with configuration information and sets up the configuration information to allocate sequentially primary data and secondary data of the write data, which are written out to a k
th
region (k=1~n) of a disk device, to the k
th
cache memory module, and a non-k
th
cache memory module, respectively.
Moreover, the present invention comprises a method and a computer-readable medium which, when executed by a computer, causes the computer to execute the processes comprising storing in n (n>2) cache memory modules of an input/output control device data received in a write request from a processing device, transmitting by the input/output control device to the processing device a write request complete response, and, asynchronously with transmitting the write request complete response, storing the data from the cache memory modules to one or more disk devices, dividing by the input/output processing device the regions of the one or more disk devices into a number of n of the cache memory modules in accordance with configuration information, and modifying by the input/output control device the configuration information to allocate sequentially primary data and secondary data of the write data, which are written out to a k
th
region (k=1~n) of a disk device, to the k
th
cache memory module, and a non-k
th
cache memory module, respectively.
These together with other objects and advantages which will be subsequently apparent, reside in the details of construction and operation as more fully hereinafter described and claimed, reference being had to the accompanying drawings forming a part hereof, wherein like numerals refer to like parts throughout.
REFERENCES:
patent: 5412668 (1995-05-01), Dewey
patent: 5615329 (1997-03-01), Kern et al.
patent: 5917999 (1999-06-01), Yamamoto et al.
patent: 6041396 (2000-03-01), Widigen
patent: 6341331 (2002-01-01), McNutt
patent: 6457098 (2002-09-01), DeKoning et al.
patent: 6460122 (2002-10-01), Otterness et al.
patent: 7-281959 (1995-10-01), None
patent: 8-087450 (1996-04-01), None
patent: 10-074129 (1998-03-01), None
Kato Tadaomi
Kubota Hiromi
Omura Hideaki
Chace Christian P.
Fujitsu Limited
Yoo Do Hyun
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